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Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2.
However, (especailly in secure boot mode), some bus attributes should be
changed from defaults before the MSS CPU tries to access shared resources.
This patch starts to use CP MSS SRAM for FW load in both secure and
non-secure boot modes.
The FW loader inserts a magic number into MSS SRAM as an indicator of
successfully loaded FS during the BL2 stage and skips releasing the MSS
CPU from the reset state.
Then, at BL31 stage, the MSS CPU is released from reset following the
call to cp110_init function that handles all the required bus attributes
configurations.

Change-Id: Idcf81cc350a086835abed365154051dd79f1ce2e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46890

Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>

Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2
definition.
Images build with MSS_SUPPORT=0 will not include service CPUs
FW and will not support PM, FC and other features implemented
in these FW images.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Idf301ebd218ce65a60f277f3876d0aeb6c72f105
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/37769

Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>

The configuration space of each standalone CP was updated in BL31.
Loading FW procedure take places earlier in SCP_BL2.
It needs to be done after access to each CP is provided.
Moving the proper configuration from BL31 to BL2 solves it.

Change-Id: I44cf88dfd4ebf09130544332bfdd3d16ef2674ea
Signed-off-by: Ben Peled <bpeled@marvell.com>

This commit introduces two changes:
- remove hardcoded references to mci0 from the driver
- perform mci optimization for all mci interfaces

It fixes performance issues observed on cn9132 CP2.

Change-Id: I4e040cd54ff95c9134035ac89b87d8feb28e9eba
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

The mci_initialize function name was misleading. The function itself
doesn't initialize MCI in general but performs MCI link tuning for
performance improvement.

Change-Id: I13094ad2235182a14984035bbe58013ebde84a7e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

Change-Id: Id702c070c433f8439faad115830e71b2873ab70a
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

By default all external CPs start with configuration address space set to
0xf200_0000. To overcome this issue, go in the loop and initialize the
CP one by one, using temporary window configuration which allows to access
each CP and update its configuration space according to decoding
windows scheme defined for each platform.

In case of cn9130 after this procedure bellow addresses will be used:
CP0 - f2000000
CP1 - f4000000
CP2 - f6000000

When the re-configuration is done there is need to restore previous
decoding window configuration(init_io_win).

Change-Id: I1a652bfbd0bf7106930a7a4e949094dc9078a981
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
plat, include/plat) are moved to the new "armada" sub-folder.

Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca339

 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Define the RT service space as secure with use of memory controller
trustzone feature. Thanks to this protection, any NS-Bootloader nor NS-OS,
won't be able to access RT services (e.g. accidentally overwrite it,
which will at best result in RT services unavailability).

Change-Id: Ie5b6cbe9a1b77879d6d8f8eac5d4e41e468496ce
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

Rename a8k_common.h to armada_common.h to keep the same header
name across all other Marvell Armada platforms.
This is especially useful since various Marvell platforms may
use common platform files and share the driver modules.

Change-Id: I7262105201123d54ccddef9aad4097518f1e38ef
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

Add common Marvell ARMADA platform components.
This patch also includes common components for Marvell
ARMADA 8K platforms.

Change-Id: I42192fdc6525a42e46b3ac2ad63c83db9bcbfeaf
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>