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This patch sets the Memory Controller's TXN_OVERRIDE registers
for most write clients to CGID_ADR. This ensures ordering is maintained.
In some cases WAW ordering problems could occur. There are different
settings for Tegra version A01 v A02.

Original changes by Alex Waterman <alexw@nvidia.com>

Change-Id: I82ea02afa43a24250ed56985757b83e78e71178c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch programs the Memory controller's control registers
to disable non-secure accesses to the TZRAM. In case these
registers are already programmed by the BL2/BL30, then the
driver just bails out.

Change-Id: Ia1416988050e3d067296373060c717a260499122
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch adds driver for the Memory Controller (v2) in the newer
Tegra SoCs. The newer hardware uses ARM's SMMU hardware instead of
the proprietary block in the past.

Change-Id: I78359da780dc840213b6e99954e45e34428d4fff
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>