- 28 Jan, 2020 1 commit
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Madhukar Pappireddy authored
This flag warns if anything is declared more than once in the same scope, even in cases where multiple declaration is valid and changes nothing. Consequently, this patch also fixes the issues reported by this flag. Consider the following two lines of code from two different source files(bl_common.h and bl31_plat_setup.c): IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE); The IMPORT_SYM macro which actually imports a linker symbol as a C expression. The macro defines the __RO_START__ as an extern variable twice, one for each instance. __RO_START__ symbol is defined by the linker script to mark the start of the Read-Only area of the memory map. Essentially, the platform code redefines the linker symbol with a different (relevant) name rather than using the standard symbol. A simple solution to fix this issue in the platform code for redundant declarations warning is to remove the second IMPORT_SYM and replace it with following assignment static const unsigned long BL2_RO_BASE = BL_CODE_BASE; Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 22 Jan, 2020 1 commit
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Anthony Steinhauser authored
Even though ERET always causes a jump to another address, aarch64 CPUs speculatively execute following instructions as if the ERET instruction was not a jump instruction. The speculative execution does not cross privilege-levels (to the jump target as one would expect), but it continues on the kernel privilege level as if the ERET instruction did not change the control flow - thus execution anything that is accidentally linked after the ERET instruction. Later, the results of this speculative execution are always architecturally discarded, however they can leak data using microarchitectural side channels. This speculative execution is very reliable (seems to be unconditional) and it manages to complete even relatively performance-heavy operations (e.g. multiple dependent fetches from uncached memory). This was fixed in Linux, FreeBSD, OpenBSD and Optee OS: https://github.com/torvalds/linux/commit/679db70801da9fda91d26caf13bf5b5ccc74e8e8 https://github.com/freebsd/freebsd/commit/29fb48ace4186a41c409fde52bcf4216e9e50b61 https://github.com/openbsd/src/commit/3a08873ece1cb28ace89fd65e8f3c1375cc98de2 https://github.com/OP-TEE/optee_os/commit/abfd092aa19f9c0251e3d5551e2d68a9ebcfec8a It is demonstrated in a SafeSide example: https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c Signed-off-by: Anthony Steinhauser <asteinhauser@google.com> Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f
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- 15 Jan, 2020 1 commit
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Marek Vasut authored
Add missing #address-cells and #size-cells into generated DT, otherwise the DT is invalid. While the parsers thus far handled this correctly via various fallbacks, this is not applicable in the long run, so fix this. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ic808a3b27b93e5258ec1a19acc3d593e53625c15
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- 06 Jan, 2020 2 commits
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Marek Vasut authored
Pass DT to OpTee OS, so that OpTee OS can extract NSEC RAM layout from the DT. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I7d5ebae8d7ab9c70f079e30563d66bbd6a8ac7a4
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Marek Vasut authored
Now that DDR drivers are mostly cleaned up , move them out of staging. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I9de63f847a0ef9ac27a79fb0f848c351fd7f4da6
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- 19 Nov, 2019 1 commit
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Justin Chadwell authored
Variable shadowing is, according to the C standard, permitted and valid behaviour. However, allowing a local variable to take the same name as a global one can cause confusion and can make refactoring and bug hunting more difficult. This patch moves -Wshadow from WARNING2 into the general warning group so it is always used. It also fixes all warnings that this introduces by simply renaming the local variable to a new name Change-Id: I6b71bdce6580c6e58b5e0b41e4704ab0aa38576e Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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- 29 Aug, 2019 2 commits
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Marek Vasut authored
The ddr_a and ddr_b register macros are the same for the most part, unify them into a single header. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I8f55d6d779837215339ac0010e8c8ab5f6748d75
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Marek Vasut authored
Do minor coding style changes to the common DDR init code to make it checkpatch compliant and move macros out into rcar_def.h. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I67eadf8099e4ff8702105c9e07b13f308d9dbe3d
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- 16 Aug, 2019 2 commits
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Marek Vasut authored
Rename RCAR_PRODUCT_* to PRR_PRODUCT_* and drop the duplicate RCAR_PRODUCT_* macro. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I6b2789790b85edb79c026f0860d70f323d113d96
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Marek Vasut authored
Pull out the PRR_* macros into rcar_def.h and remove multiple copies of it. Now that there are still RCAR_* macros in rcar_def.h too and they have the exact same meaning as the PRR_* macros, but that's for another patch. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Icb7f61b971b1a23102bd1b9f58cda580660a55fc
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- 01 Aug, 2019 1 commit
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Julius Werner authored
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__. All common C compilers predefine a macro called __ASSEMBLER__ when preprocessing a .S file. There is no reason for TF-A to define it's own __ASSEMBLY__ macro for this purpose instead. To unify code with the export headers (which use __ASSEMBLER__ to avoid one extra dependency), let's deprecate __ASSEMBLY__ and switch the code base over to the predefined standard. Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417 Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 12 Jul, 2019 1 commit
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Toshiyuki Ogasahara authored
Update the revision number in the revision management file. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I94acd1bb53d9d2453e550e2a13b6391b9088ff8d
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- 11 Jul, 2019 1 commit
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Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I51278beacbe6da79853c3f0f0f94cd806fc9652c Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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- 22 Jun, 2019 1 commit
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Marek Vasut authored
Now that PFC drivers are cleaned up , move them out of staging. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ie594b53558c2bfb8e5d88e5b0354752c17a2487e
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- 17 Jun, 2019 1 commit
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Marek Vasut authored
Now that QoS drivers are cleaned up , move them out of staging. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: If61ab2157c30b8f5a6b91d2c56ddbb9098ef99e8
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- 13 Jun, 2019 1 commit
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Marek Vasut authored
Convert the R-Car Gen3 platform and both SCIF and Log drivers to multi-console API. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I18556973937d150b60453f9150d54ee612571e35
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- 11 Apr, 2019 4 commits
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Toshiyuki Ogasahara authored
Update the revision number in the revision management file. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: If8918efad0fcbe6f91b66c0c7438406b1d4fb759
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Toshiyuki Ogasahara authored
Changed to save and restore cntpct_el0 using memory mapped register for generic timer when System Suspend and Resume. Reported by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I40fd9f5434c4d52b320cd1d20322b9b8e4e67155
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Toshiyuki Ogasahara authored
Update the revision number in the revision management file. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I239f4d9f58d38515a49fa1a22cece48b59710d15
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Toshiyuki Ogasahara authored
Periodic write DQ training available as default. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I649cfe538e4e2c7e19145ce7d1938ce4361b2529
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- 02 Apr, 2019 3 commits
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Valentine Barshak authored
Add R-Car V3M support. This is based on the original V3M support patch for Yocto v2.23.1 by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> --- Marek: Update on top of mainline ATF/master
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Marek Vasut authored
Add R-Car D3 SoC platform specifics. Driver, PFC, QoS, DDR init code will be added separately. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Print the DRAM bank size in MiB instead of GiB in case the bank size is smaller than 1 GiB. This prevents printing zeroes on systems with small DRAM sizes. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 26 Mar, 2019 1 commit
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Marek Vasut authored
The M3W ULCB board has 2 GiB of DRAM, set it so. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 04 Mar, 2019 1 commit
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Marek Vasut authored
Add support for the M3W 3.0 SoC and synchronize the upstream ATF with Renesas downstream ATF release v2.0.1. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 20 Feb, 2019 1 commit
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Marek Vasut authored
In case the PCIe controller receives a L1_Enter_PM DLLP, it will disable the internal PLLs. The system software cannot predict it and can attempt to perform device config space access across the PCIe link while the controller is in this transitional state. If such condition happens, the PCIe controller register access will trigger ARM64 SError exception. This patch adds checks for which PCIe controller is enabled, checks whether the PCIe controller is in such a transitional state and if so, first completes the transition and then restarts the instruction which caused the SError. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 01 Feb, 2019 1 commit
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Antonio Nino Diaz authored
Also, update platform_def.h guidelines about includes in the porting guide. Change-Id: I1ae338c9dd3242b309f6d53687ba2cb755d488c3 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 29 Jan, 2019 4 commits
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Marek Vasut authored
The ATF code fails to build with PMIC_ROHM_BD9571=0, add the missing function into the PWRC code. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Allow auto-detecting E3 when RCAR_LSI is set to RCAR_AUTO. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
The macro is not used, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
This reverts commit d48536e2 , which misbehaves on R-Car H3 ES2.0. Until the reason for that misbehavior is understood, revert the commit. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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- 08 Jan, 2019 9 commits
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Marek Vasut authored
Update the reported Renesas version to 2.0.0, since the DDR/QoS/PFC table versions match the ones from that release. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Replace the ad-hoc implementation of delay in PWRC driver with common R-Car delay code. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Rewrite the delay code from assembler to C. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Add code to determine the platform timer frequency and configure the generic timer accordingly early in BL2. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Move the rcar_cpld_reset_cpu() function into header file and zap the externs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Since the interrupts are handled in EL3, dump the EL3 error registers in case an error happens. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
The reset address is programmable on the R-Car Gen3, enable it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Disable the IPMMU PV0 cache on E3 rev. 1.x . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Add support for R-Car E3 silicon rev. 1.1 Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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