- 28 Nov, 2019 3 commits
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Hadi Asyrafi authored
Pull out mailbox driver into common area as they can be shared between intel's socfpga platform Signed-off-by:Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4064de1ec668931d77abcb7804f6952b70d33716
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Hadi Asyrafi authored
Share socfpga private definitions and storage driver between Agilex and Stratix 10 platform. Signed-off-by: -
Hadi Asyrafi authored
Pull out handoff driver to intel/soc/ common directory as they can be shared by both Agilex and Stratix10 platform. Share platform_def header between both Agilex and Stratix10 and store platform specific definitions in socfpga_plat_def.h Signed-off-by:
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- 13 Aug, 2019 1 commit
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Hadi Asyrafi authored
Extract clock information for UART, MMC & Watchdog from the platform rather than hard code it Signed-off-by:
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- 07 Aug, 2019 1 commit
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Hadi Asyrafi authored
Pull out common code from aarch64 and include Signed-off-by:
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- 26 Jun, 2019 1 commit
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Hadi Asyrafi authored
Signed-off-by:
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- 21 Mar, 2019 1 commit
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Muhammad Hadi Asyrafi Abdul Halim authored
Watchdog driver support & enablement during platform setup Signed-off-by:
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- 13 Mar, 2019 1 commit
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Muhammad Hadi Asyrafi Abdul Halim authored
Manages QSPI initialization, configuration and IO handling as boot device Signed-off-by:
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- 08 Mar, 2019 2 commits
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Tien Hock, Loh authored
MMC stack needs OCR voltage information for the platform to initialize MMC controller correctly. Signed-off-by:Tien Hock, Loh <tien.hock.loh@intel.com>
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Tien Hock, Loh authored
MMC stack needs OCR voltage information for the platform to initialize MMC controller correctly. Signed-off-by:
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- 07 Mar, 2019 1 commit
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Muhammad Hadi Asyrafi Abdul Halim authored
Change map region for device 2 from non-secure to secure Signed-off-by:
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- 13 Feb, 2019 1 commit
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Loh Tien Hock authored
A DDR calibration value is missing write mask, causing ECC DDR calibration to fail. This patch addresses the issue. ECC should also be scrubbed before MMU initializes, thus the scrubbing is moved to ddr intialization phase. Signed-off-by:
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- 04 Feb, 2019 1 commit
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Loh Tien Hock authored
This adds BL2 support for Intel Stratix 10 SoC FPGA. Functionality includes: - Release and setup peripherals from reset - Calibrate DDR - ECC DDR Scrubbing - Load FIP (bl31 and bl33) Signed-off-by:
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