- 11 Feb, 2021 2 commits
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Konstantin Porotchkin authored
- Add setup of DMA stream IDs in AP807/AP806 drivers Change-Id: I23ffe86002db4753f812c63c31431a3d04056d07 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
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Konstantin Porotchkin authored
Add initialization for TRNG-IP-76 driver and support SMC call 0xC200FF11 used for reading HW RNG value by secondary bootloader software for KASLR support. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Change-Id: I1d644f67457b28d347523f8a7bfc4eacc45cba68 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/32688 Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Ofer Heifetz <oferh@marvell.com>
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- 03 Jun, 2020 1 commit
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Marcin Wojtas authored
This patch enables the stream ID for the SD/MMC controllers via dedicated unit register. Thanks to this change it is possible to configure properly the IOMMU in OS and use the SD/MMC interface in a guest Virtual Machine. Change-Id: I99cbd2c9882eb558ba01405d3d8a3e969f06e082 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
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- 30 Jan, 2020 1 commit
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Grzegorz Jaszczyk authored
In order to access MG SRAM, the amb bridge needs to be configured which is done in bl2 platform init. For MG CM3, the image is only loaded to its SRAM and the CM3 itself is left in reset. It is because the next stage bootloader (e.g. u-boot) will trigger action which will take it out of reset when needed. This can happen e.g. when appropriate device-tree setup (which has enabled 802.3 auto-neg) will be chosen. In other cases the MG CM3 should not be running. Change-Id: I816ea14e3a7174eace068ec44e3cc09998d0337e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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- 11 Jul, 2019 1 commit
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Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I78f386f5ac171d6e52383a3e42003e6fb3e96b57 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 03 Sep, 2018 1 commit
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Marcin Wojtas authored
It turned out that resetting the RTC time register is not necessary during initial configuration. Safely remove it from the sequence. Change-Id: Id2b9c7db44a8c8dbe88a7f8a21695b72a7fd78ee Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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- 18 Jul, 2018 1 commit
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Konstantin Porotchkin authored
Add ModularChip and MCI drivers for A8K SoC family. ModularChip drivers include support for the internal building blocks of Marvell ARMADA SoCs - APN806, APN807 and CP110 Change-Id: I9559343788fa2e5eb47e6384a4a7d47408787c02 Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
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