- 22 Aug, 2018 9 commits
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Antonio Nino Diaz authored
The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers. Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: I4f58bb4660078c9bc76d2826c90b2fa711719a3e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Remove code specific to FreeBSD so that they can be used in this repository. Change-Id: I5c11eb5b3c05a7fb91aed08371a1f7a0e6122a94 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
From commit aafd1cf4235d78ce85b76d7da63e9589039344b3: - sys/sys/endian.h - sys/arm/include/endian.h - sys/arm64/include/endian.h - sys/sys/errno.h - lib/libc/strchr.c - lib/libc/strcmp.c - lib/libc/strncmp.c - lib/libc/strnlen.c strcasecmp() hasn't been imported. Change-Id: I8a0787aec9ba8960a008fb5c66f7a73c84919b93 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: I76091d52571f1950111c4b1670d5fc3883607715 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
The existing files had some style problems that this patch fixes. Change-Id: I794e0d96e52f8da0ffa0d70a41f36c4432b4e563 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
They are too big for the Trusted Firmware, and it can be confusing to have two versions of the same functions with different names. tf_printf and tf_snprintf will replace them in the next patch. Change-Id: I978414ac169cc3156e249549ef101a70eb31a295 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
sscanf() is unused and it doesn't work, so it doesn't make sense to keep it. timingsafe_bcmp() isn't used anywhere. Change-Id: Ib5d28ff21d0f3ccc36c5c0fb5474b3384105cf80 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Remove all files that don't have only Arm copyright. This is the first step to cleanup the C library in this repository. They will be re-added in the following patches. Change-Id: I72c40a1620d1df3228fc397ec695d569a20245fd Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 20 Aug, 2018 2 commits
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Jeenu Viswambharan authored
These changes address most of the required MISRA rules. In the process, some from generic code is also fixed. No functional changes. Change-Id: I76cacf6e1d73b09510561b5090c2bb66d81bec88 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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Jeenu Viswambharan authored
Memory Partitioning And Monitoring is an Armv8.4 feature that enables various memory system components and resources to define partitions. Software running at various ELs can then assign themselves to the desired partition to control their performance aspects. With this patch, when ENABLE_MPAM_FOR_LOWER_ELS is set to 1, EL3 allows lower ELs to access their own MPAM registers without trapping to EL3. This patch however doesn't make use of partitioning in EL3; platform initialisation code should configure and use partitions in EL3 if required. Change-Id: I5a55b6771ccaa0c1cffc05543d2116b60cbbcdcd Co-authored-by: James Morse <james.morse@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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- 17 Aug, 2018 2 commits
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Varun Wadekar authored
This patch uses the 'declare_cpu_ops_wa' macro, to set the check function, to report that Denver cores are mitigated. Denver cores are vulnerable to this anomaly and require the mitigation to be enabled always. Change-Id: I1bb6eefdec8c01fb8b645e112f8d04d4bb8811ef Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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John Tsichritzis authored
If the system is in near idle conditions, this erratum could cause a deadlock or data corruption. This patch applies the workaround that prevents this. This DSU erratum affects only the DSUs that contain the ACP interface and it was fixed in r2p0. The workaround is applied only to the DSUs that are actually affected. Link to respective Arm documentation: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.epm138168/index.html Change-Id: I033213b3077685130fc1e3f4f79c4d15d7483ec9 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 10 Aug, 2018 1 commit
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Antonio Nino Diaz authored
The translation library is useful elsewhere. Even though this repository doesn't exercise the EL2 support of the library, it is better to have it here as well to make it easier to maintain. enable_mmu_secure() and enable_mmu_direct() have been deprecated. The functions are still present, but they are behind ERROR_DEPRECATED and they call the new functions enable_mmu_svc_mon() and enable_mmu_direct_svc_mon(). Change-Id: I13ad10cd048d9cc2d55e0fff9a5133671b67dcba Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 07 Aug, 2018 1 commit
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Antonio Nino Diaz authored
During cold boot, the initial translation tables are created with data caches disabled, so all modifications go to memory directly. After the MMU is enabled and data cache is enabled, any modification to the tables goes to data cache, and eventually may get flushed to memory. If CPU0 modifies the tables while CPU1 is off, CPU0 will have the modified tables in its data cache. When CPU1 is powered on, the MMU is enabled, then it enables coherency, and then it enables the data cache. Until this is done, CPU1 isn't in coherency, and the translation tables it sees can be outdated if CPU0 still has some modified entries in its data cache. This can be a problem in some cases. For example, the warm boot code uses only the tables mapped during cold boot, which don't normally change. However, if they are modified (and a RO page is made RW, or a XN page is made executable) the CPU will see the old attributes and crash when it tries to access it. This doesn't happen in systems with HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY. In these systems, the data cache is enabled at the same time as the MMU. As soon as this happens, the CPU is in coherency. There was an attempt of a fix in psci_helpers.S, but it didn't solve the problem. That code has been deleted. The code was introduced in commit <26441030 > ("Invalidate TLB entries during warm boot"). Now, during a map or unmap operation, the memory associated to each modified table is flushed. Traversing a table will also flush it's memory, as there is no way to tell in the current implementation if the table that has been traversed has also been modified. Change-Id: I4b520bca27502f1018878061bc5fb82af740bb92 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 06 Aug, 2018 1 commit
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Antonio Nino Diaz authored
Changed the names for consistency with the rest of the library. Introduced new helpers that manipulate the active translation tables context. Change-Id: Icaca56b67fcf6a96e88aa3c7e47411162e8e6856 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 03 Aug, 2018 4 commits
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Roberto Vargas authored
Romlib is a new image that is stored in ROM and contains the code of several libraries that can be shared between different images. All the functions within in the library are accessed using a jump table which allows to update the romlib image whithout changing the binary compatibility. This jump table can be also stored in RAM and it can allow to patch a romlib with potential bugs fixes.. Change-Id: If980ccdaca24b7aaca900e32acc68baf6f94ab35 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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Roberto Vargas authored
We had exit but we didn't have atexit, and we were calling panic and tf_printf from exit, which generated a dependency from exit to them. Having atexit allows to set a different function pointer in every image. Change-Id: I95b9556d680d96249ed3b14da159b6f417da7661 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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Roberto Vargas authored
TF Makefile was linking all the objects files generated for the c library instead of creating a static library that could be used in the linking stage. Change-Id: I721daea097e9b13cbb42c9f8eaa2af8fea0799cf Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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Roberto Vargas authored
TF Makefile was linking all the objects files generated for the fdt library instead of creating a static library that could be used in the linking stage. Change-Id: If3705bba188ec39e1fbf2322a7f2a9a941e1b90d Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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- 02 Aug, 2018 2 commits
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Antonio Nino Diaz authored
Change-Id: I77c9cd2d1d6d0122cc49917fa686014bee154589 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Change-Id: I35d5b6a7c219f6f38983b30f157c1ed3808af17f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 30 Jul, 2018 1 commit
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Antonio Nino Diaz authored
Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6, 14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9. Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9765bd Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 26 Jul, 2018 2 commits
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Andrew F. Davis authored
If either USE_COHERENT_MEM or HW_ASSISTED_COHERENCY being true should cause us to not enter the ifdef block, then the logic is not correct here. Posibly bad use of De Morgan's law? Fix this. Signed-off-by: Andrew F. Davis <afd@ti.com>
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Sughosh Ganu authored
Add a null pointer check for the error record probe function -- avoids a panic in case a platform has not defined it. Change-Id: I1139fa0df33297a12ec16615cacd07540925f991 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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- 24 Jul, 2018 4 commits
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Antonio Nino Diaz authored
MISRA C-2012 Rules 10.1, 10.3, 17.8 and 20.7. Change-Id: I3980bd2a1d845559af4bbe2887a0250d0506a064 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
MISRA C-2012 Rules 10.1, 10.3 and 20.7. Change-Id: I972ce63f0d8fa157ed17e826b84f218fe498c517 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
MISRA C-2012 Rules 10.1 and 10.3. Change-Id: I88cd5f56cda5780f2e0ba541c0f5b561309ab3af Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Fix violations of MISRA C-2012 Rules 8.13, 10.1, 10.3, 17.7 and 20.7. Change-Id: I6f45a1069b742aebf9e1d6a403717b1522083f51 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 20 Jul, 2018 3 commits
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Antonio Nino Diaz authored
Also change header guards to fix defects of MISRA C-2012 Rule 21.1. Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Fix MISRA C-2012 Directive 4.9 defects. Change-Id: Ibd5364d8f138ddcf59c8074c32b35769366807dc Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Fix MISRA C-2012 Directive 4.9 and Rule 21.1 defects. Change-Id: I96c216317d38741ee632d2640cd7b36e6723d5c2 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 15 Jul, 2018 2 commits
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Antonio Nino Diaz authored
This library can be used in other projects. All comments that talk about the Trusted Firmware should be talking about the library itself. Change-Id: I3b98d42f7132be72c1f8a4900acfaa78dbd2daa2 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
This allows other parts of the code to reuse it. No functional changes. Change-Id: Ib052ae235c422d9179958bd3016c3e678779ae9b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 13 Jul, 2018 4 commits
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Antonio Nino Diaz authored
Most registers are 64-bit wide, even in AArch32 mode: - MAIR_ELx is equivalent to MAIR0 and MAIR1. - TTBR is 64 bit in both AArch64 and AArch32. The only difference is the TCR register, which is 32 bit in AArch32 and in EL3 in AArch64. For consistency with the rest of ELs in AArch64, it makes sense to also have it as a 64-bit value. Change-Id: I2274d66a28876702e7085df5f8aad0e7ec139da9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
The Exception Level is now detected at runtime. This means that it is not needed to hardcode the EL used by each image. This doesn't result in a substantial increase of the image size because the initialization functions that aren't used are garbage-collected by the linker. In AArch32 the current EL has been changed from EL3 to EL1 because the the AArch32 PL1&0 translation regime behaves more like the AArch64 EL1&0 translation regime than the EL3 one. Change-Id: I941404299ebe7666ca17619207c923b49a55cb73 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
xlat_arch_tlbi_va_regime() isn't used, so it has been renamed to xlat_arch_tlbi_va() and the previous implementation has been removed. Change-Id: Ic118bed3fb68234748d86b2e9e95b25650289276 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
They only contained one function that is easily integrated in the private library header and the existing architectural C files. This also helps making the library more portable, as the Makefile of the library now doesn't use the variable INCLUDES, which is specific to this codebase and doesn't respect the namespace of the library. Change-Id: I22228e6a97e9b4f346f5cd8947609263e8df71d8 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 11 Jul, 2018 2 commits
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Joel Hutton authored
Change-Id: Ic0486131c493632eadf329f80b0b5904aed5e4ef Signed-off-by: Joel Hutton <joel.hutton@arm.com> Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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Joel Hutton authored
Change-Id: I2c4b06423fcd96af9351b88a5e2818059f981f1b Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com> Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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