1. 26 Mar, 2019 1 commit
  2. 19 Mar, 2019 1 commit
  3. 18 Mar, 2019 1 commit
    • Alexei Fedorov's avatar
      Declare PAuth for Secure world as experimental · 06715f85
      Alexei Fedorov authored
      
      
      Declare ENABLE_PAUTH and CTX_INCLUDE_PAUTH_REGS
      build options as experimental.
      Pointer Authentication is enabled for Non-secure world
      irrespective of the value of these build flags if the
      CPU supports it.
      The patch also fixes the description of fiptool 'help' command.
      
      Change-Id: I46de3228fbcce774a2624cd387798680d8504c38
      Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      06715f85
  4. 14 Mar, 2019 1 commit
  5. 28 Feb, 2019 1 commit
  6. 27 Feb, 2019 3 commits
    • Varun Wadekar's avatar
      Tegra: Support for scatterfile for the BL31 image · c2ad38ce
      Varun Wadekar authored
      
      
      This patch provides support for using the scatterfile format as
      the linker script with the 'armlink' linker for Tegra platforms.
      
      In order to enable the scatterfile usage the following changes
      have been made:
      
      * provide mapping for ld.S symbols in bl_common.h
      * include bl_common.h from all the affected files
      * update the makefile rules to use the scatterfile and armlink
        to compile BL31
      * update pubsub.h to add sections to the scatterfile
      
      NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY.
      
      Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      c2ad38ce
    • Antonio Nino Diaz's avatar
      Add support for pointer authentication · b86048c4
      Antonio Nino Diaz authored
      
      
      The previous commit added the infrastructure to load and save
      ARMv8.3-PAuth registers during Non-secure <-> Secure world switches, but
      didn't actually enable pointer authentication in the firmware.
      
      This patch adds the functionality needed for platforms to provide
      authentication keys for the firmware, and a new option (ENABLE_PAUTH) to
      enable pointer authentication in the firmware itself. This option is
      disabled by default, and it requires CTX_INCLUDE_PAUTH_REGS to be
      enabled.
      
      Change-Id: I35127ec271e1198d43209044de39fa712ef202a5
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      b86048c4
    • Antonio Nino Diaz's avatar
      Add ARMv8.3-PAuth registers to CPU context · 5283962e
      Antonio Nino Diaz authored
      
      
      ARMv8.3-PAuth adds functionality that supports address authentication of
      the contents of a register before that register is used as the target of
      an indirect branch, or as a load.
      
      This feature is supported only in AArch64 state.
      
      This feature is mandatory in ARMv8.3 implementations.
      
      This feature adds several registers to EL1. A new option called
      CTX_INCLUDE_PAUTH_REGS has been added to select if the TF needs to save
      them during Non-secure <-> Secure world switches. This option must be
      enabled if the hardware has the registers or the values will be leaked
      during world switches.
      
      To prevent leaks, this patch also disables pointer authentication in the
      Secure world if CTX_INCLUDE_PAUTH_REGS is 0. Any attempt to use it will
      be trapped in EL3.
      
      Change-Id: I27beba9907b9a86c6df1d0c5bf6180c972830855
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      5283962e
  7. 08 Feb, 2019 3 commits
  8. 05 Feb, 2019 1 commit
  9. 31 Jan, 2019 1 commit
  10. 30 Jan, 2019 1 commit
  11. 29 Jan, 2019 1 commit
  12. 15 Jan, 2019 1 commit
    • Paul Beesley's avatar
      Correct typographical errors · 8aabea33
      Paul Beesley authored
      
      
      Corrects typos in core code, documentation files, drivers, Arm
      platforms and services.
      
      None of the corrections affect code; changes are limited to comments
      and other documentation.
      
      Change-Id: I5c1027b06ef149864f315ccc0ea473e2a16bfd1d
      Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
      8aabea33
  13. 17 Dec, 2018 1 commit
    • Soby Mathew's avatar
      docs: User-guide corrections for RESET_TO_BL31 · 8aa4e5f4
      Soby Mathew authored
      
      
      This patch updates the user guide instructions for
      RESET_TO_SP_MIN and RESET_TO_BL31 cases. The load
      address for BL31 had to be updated because of increase
      in code size. Also, information about PIE support when
      RESET_TO_BL31=1 for FVP is added.
      
      In the case of RESET_TO_SP_MIN, the RVBAR address
      was wrong in the instruction. This is also corrected
      in the patch.
      
      Change-Id: I65fe6d28c5cf79bee0a11fbde320d49fcc1aacf5
      Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      8aa4e5f4
  14. 05 Nov, 2018 1 commit
  15. 29 Oct, 2018 1 commit
  16. 10 Oct, 2018 1 commit
  17. 02 Oct, 2018 1 commit
    • Antonio Nino Diaz's avatar
      plat/arm: Remove option ARM_BOARD_OPTIMISE_MEM · c0740e4f
      Antonio Nino Diaz authored
      
      
      This option makes it hard to optimize the memory definitions of all Arm
      platforms because any change in the common defines must work in all of
      them. The best thing to do is to remove it and move the definition to
      each platform's header.
      
      FVP, SGI and SGM were using the definitions in board_arm_def.h. The
      definitions have been copied to each platform's platform_def.h. Juno
      was already using the ones in platform_def.h, so there have been no
      changes.
      
      Change-Id: I9aecd11bbc72a3d0d7aad1ef9934d8df21dcfaf2
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      c0740e4f
  18. 01 Oct, 2018 1 commit
  19. 28 Sep, 2018 4 commits
  20. 20 Sep, 2018 2 commits
  21. 11 Sep, 2018 1 commit
  22. 30 Aug, 2018 3 commits
    • Douglas Raillard's avatar
      backtrace: Introduce backtrace function · 0c62883f
      Douglas Raillard authored
      
      
      This function diplays the backtrace, the current EL and security state
      to allow a post-processing tool to choose the right binary to interpret
      the dump.
      
      The output can be fed to GNU addr2line to resolve function names given
      an ELF binary compiled with debug information. The "-i" flag is
      recommended to improve display in case of inlined functions. The *.dump
      files generated during the build process can also be used.
      
      The function works in AArch64 and AArch32. In AArch32 it only works in
      A32 mode (without T32 interworking), which is enforced in the Makefile.
      
      Sample output of a backtrace at EL3:
      
          BACKTRACE: START: function_name
          0: EL3: 0x798
          1: EL3: 0x538
          2: EL3: 0x550
          3: EL3: 0x55c
          4: EL3: 0x568
          5: EL3: 0x5a8
          6: EL3: 0xf4
          BACKTRACE: END: function_name
      
      In order to enable it the new option ENABLE_BACKTRACE must be set to 1.
      This option is set to 1 by default only in AArch64 debug builds. As
      usual, it can be overridden by the platform makefile and in the build
      command line.
      
      Change-Id: Icaff39b0e5188329728be2f3c72b868b2368e794
      Co-authored-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      Signed-off-by: default avatarDouglas Raillard <douglas.raillard@arm.com>
      0c62883f
    • Antonio Nino Diaz's avatar
      Allow manually setting the AArch32 instruction set · 8fd9d4d5
      Antonio Nino Diaz authored
      
      
      At the moment the AArch32 instruction set isn't specified in the command
      line, which means that the compiler is free to choose the one it sees
      fit. This decision may change between compiler versions, so it is better
      to specify it manually.
      
      The build option AARCH32_INSTRUCTION_SET has been introduced for this
      reason. This option can be set to T32 or A32 to pass the correct flags
      to the compiler.
      
      The current behaviour is to default to T32 due to it's smaller size.
      
      Change-Id: I02297eb1d9404b5868ff7c054fbff9b3cda7fdb6
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      8fd9d4d5
    • Julius Werner's avatar
      context_mgmt: Fix HANDLE_EA_EL3_FIRST implementation · 24f671f3
      Julius Werner authored
      This patch fixes a bug in the context management code that causes it to
      ignore the HANDLE_EA_EL3_FIRST compile-time option and instead always
      configure SCR_EL3 to force all external aborts to trap into EL3. The
      code used #ifdef to read compile-time option declared with add_define in
      the Makefile... however, those options are always defined, they're just
      defined to either 0 or 1, so #if is the correct syntax to check for
      them. Also update the documentation to match.
      
      This bug has existed since the Nov 2017 commit 76454abf
      
       (AArch64:
      Introduce External Abort handling), which changed the
      HANDLE_EA_EL3_FIRST option to use add_define.
      
      Change-Id: I7189f41d0daee78fa2fcf4066323e663e1e04d3d
      Signed-off-by: default avatarJulius Werner <jwerner@chromium.org>
      24f671f3
  23. 20 Aug, 2018 1 commit
    • Jeenu Viswambharan's avatar
      AArch64: Enable MPAM for lower ELs · 5f835918
      Jeenu Viswambharan authored
      
      
      Memory Partitioning And Monitoring is an Armv8.4 feature that enables
      various memory system components and resources to define partitions.
      Software running at various ELs can then assign themselves to the
      desired partition to control their performance aspects.
      
      With this patch, when ENABLE_MPAM_FOR_LOWER_ELS is set to 1, EL3 allows
      lower ELs to access their own MPAM registers without trapping to EL3.
      This patch however doesn't make use of partitioning in EL3; platform
      initialisation code should configure and use partitions in EL3 if
      required.
      
      Change-Id: I5a55b6771ccaa0c1cffc05543d2116b60cbbcdcd
      Co-authored-by: default avatarJames Morse <james.morse@arm.com>
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      5f835918
  24. 17 Aug, 2018 1 commit
  25. 24 Jul, 2018 1 commit
  26. 11 Jul, 2018 2 commits
  27. 10 Jul, 2018 1 commit
  28. 27 Jun, 2018 1 commit
    • Jeenu Viswambharan's avatar
      DynamIQ: Enable MMU without using stack · 64ee263e
      Jeenu Viswambharan authored
      
      
      Having an active stack while enabling MMU has shown coherency problems.
      This patch builds on top of translation library changes that introduces
      MMU-enabling without using stacks.
      
      Previously, with HW_ASSISTED_COHERENCY, data caches were disabled while
      enabling MMU only because of active stack. Now that we can enable MMU
      without using stack, we can enable both MMU and data caches at the same
      time.
      
      NOTE: Since this feature depends on using translation table library v2,
      disallow using translation table library v1 with HW_ASSISTED_COHERENCY.
      
      Fixes ARM-software/tf-issues#566
      
      Change-Id: Ie55aba0c23ee9c5109eb3454cb8fa45d74f8bbb2
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      64ee263e
  29. 22 Jun, 2018 1 commit
    • John Tsichritzis's avatar
      Fix typos in documentation · 677ad32c
      John Tsichritzis authored
      
      
      In the porting guide, there are blue boxes that describe the argument
      types and the return type of each function.  A small typo caused some of
      these boxes not being properly rendered.
      
      In the user guide, small typos were fixed that caused random text being
      unintentionally rendered as bold.  Also, a slight rewording was done in
      the section describing the DYN_DISABLE_AUTH flag.
      
      Change-Id: I57303ca609436a82162fa9b42c06b0d5a63da6df
      Signed-off-by: default avatarJohn Tsichritzis <john.tsichritzis@arm.com>
      677ad32c