- 17 Dec, 2019 3 commits
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Heiko Stuebner authored
Similar to others like rk3399 and rk3288 move the secure init to a separate file to unclutter the soc init a bit. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Change-Id: Iebb38e24f1c7fe5353f139c896fb8ca769bf9691
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Heiko Stuebner authored
The calls to secure ddr regions on rk3288 and rk3399 use parameters of base and size - as it custom for specifying memory regions, but the functions themself expect start and endpoints of the area. This only works by chance for the TZRAM, as it starts a 0x0 and therefore its end location is the same as its size. To not fall into a trap later on adapt the functions to really take base+size parameters. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Change-Id: Idb9fab38aa081f3335a4eca971e7b7f6757fbbab
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Heiko Stuebner authored
The agreed upon division of early boot locations is 0x40000 for bl31 to leave enough room for u-boot-spl and 0x100000 for bl33 (u-boot). rk3288 and rk3399 already correctly secure the ddr up to the 1MB boundary so pull the other platforms along to also give the Rockchip TF-A enough room to comfortably live in. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Change-Id: Ie9e0c927d3074a418b6fd23b599d2ed7c15c8c6f
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- 13 Dec, 2019 1 commit
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Joshua Watt authored
Instead of stringizing the paths to binary files, add them as string defines on the command line (e.g. -DFOO=\"BAR\" instead of -DFOO=BAR). This prevents macros from being expanded inside the string value itself. For example, -DFOO=/path/with-linux-in-it would have been expanded to "/path/with-1-in-it" because `linux=1` is one of the standard GCC defines. Change-Id: I7b65df3c9930faed4f1aff75ad726982ae3671e6 Signed-off-by: Joshua Watt <JPEWhacker@gmail.com>
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- 27 Nov, 2019 1 commit
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Paul Kocialkowski authored
Add the UART3 base definition for serial output, which is used on some PX30 SoM boards. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Change-Id: I8490b15c9f129a33c01cb78bd78675014bc7b015
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- 19 Nov, 2019 1 commit
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Justin Chadwell authored
Variable shadowing is, according to the C standard, permitted and valid behaviour. However, allowing a local variable to take the same name as a global one can cause confusion and can make refactoring and bug hunting more difficult. This patch moves -Wshadow from WARNING2 into the general warning group so it is always used. It also fixes all warnings that this introduces by simply renaming the local variable to a new name Change-Id: I6b71bdce6580c6e58b5e0b41e4704ab0aa38576e Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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- 17 Nov, 2019 1 commit
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Vasily Khoruzhick authored
And return NULL if we didn't get them in bl aux params otherwise reset and poweroff will be broken on platforms that do not have reset and poweroff GPIOs. Fixes: c1185ffd ("plat/rockchip: Switch to use new common BL aux parameter library") Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Change-Id: Ic6cf6383d8f05d745e2c5d5e1b1df38514ea8429
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- 20 Sep, 2019 2 commits
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Kever Yang authored
Rockchip platform is using the first 1MB of DRAM as secure ram space, and there is a vendor loader who loads and runs the BL31/BL32/BL33, this loader is usually load by SoC BootRom to the start addres of DRAM, we need to reserve enough space for this loader so that it doesn't need to do the relocate when loading the BL31. eg. We use U-Boot SPL to load ATF BL31 and U-Boot proper as BL33, the SPL TEXT BASE is offset 0 of DRAM which is decide by Bootrom; if we update the BL31_BASE to offset 0x40000(256KB), then the 0~0x40000 should be enough for SPL and no need to do the relocate while the space size 0x10000(64KB) may not enough for SPL. After this update, the BL31 can use the rest 768KB of the first 1MB, which is also enough, and the loader who is using BL31 elf file can support this update without any change. Change-Id: I66dc685594d77f10f9a49c3be015fd6729250ece Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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Kever Yang authored
The 'txet' should be 'text'. Change-Id: I2217a1adf50c3b86f3087b83c77d9291b280627c Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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- 09 Aug, 2019 2 commits
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Heiko Stuebner authored
The rk3399 suspend code saves and restores the debug uart settings, but right now always does this for the default uart. Right now this works only by chance for the majority of rk3399 boards, which do not deviate from that default. But both Coreboot as well as U-Boot-based platforms can actually use different uarts for their output, which can be configured from either devicetree or Coreboot-variables. To fix this, just use the stored uart-base information instead of the default constant. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I1ea059d59a1126f6f8702315df7e620e632b686e
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Heiko Stuebner authored
Rockchip platforms can be booted from either u-boot or coreboot. So far the Coreboot-console was initizalized from a coreboot data struct in the early_param2 callbacks and dt-based consoles with data from the rockchip_get_uart_* functions. But later code may also need this console information for example for special suspend handling. To make this easy follow a suggestion from Julius Werner and move the coreboot<->dt distinction into the rockchip_get_uart_* functions, thus making correct data about the used uart available to all Rockchip platform code at all times. This includes a new rockchip_get_uart_clock as well, because while the dt-platforms right now always just default the rate defined in a constant Coreboot provides its own field for the clock rate and we don't want to loose that information for the console init. Similarly the rk_uart_* variables should move into the non-Coreboot code, to prevent them from being marked as unused, which also requires the rk_get_uart_* functions to move below the actual dt-parsing. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I278d595d2aa6c6864187fc8979a9fbff9814feac
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- 05 Aug, 2019 2 commits
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Heiko Stuebner authored
A previous patch already allowed to configure the uart output from the devicetree, but on Rockchip platforms we also have the issue of different vendors using different baudrates for their uarts. For example, rk3399 has a default baudrate of 115200 which is true for ChromeOS-devices and boards from Theobroma-Systems, while all the boards using the vendor boot chain actually use a baudrate of 1500000. Similarly the newly added px30 has a default of said 1500000 but some boards may want to use the more widely used 115200. The devicetree stdout-path node already contains the desired baudrate, so add simple code to parse it from there and override the default, which stays unchanged. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I7412139c3df3073a1996eb508ec08642ec6af90d
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Heiko Stuebner authored
The px30 mini-evb can use either uart2 (muxed with the sd-card pins) or uart5 via its pin header for serial output. Uart5 is especially useful when needing to boot from the sd-card, where uart2 obviously is not useable. So add the uart5 constants and it as uart option for the serial-param handler. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: Ib88df7a55d761ee104d312c9953a13de3beba1c4
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- 01 Aug, 2019 2 commits
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Julius Werner authored
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__. All common C compilers pre-define the same macros to signal which architecture the code is being compiled for: __arm__ for AArch32 (or earlier versions) and __aarch64__ for AArch64. There's no need for TF-A to define its own custom macros for this. In order to unify code with the export headers (which use __aarch64__ to avoid another dependency), let's deprecate the AARCH32 and AARCH64 macros and switch the code base over to the pre-defined standard macro. (Since it is somewhat unintuitive that __arm__ only means AArch32, let's standardize on only using __aarch64__.) Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200 Signed-off-by: Julius Werner <jwerner@chromium.org>
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Julius Werner authored
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__. All common C compilers predefine a macro called __ASSEMBLER__ when preprocessing a .S file. There is no reason for TF-A to define it's own __ASSEMBLY__ macro for this purpose instead. To unify code with the export headers (which use __ASSEMBLER__ to avoid one extra dependency), let's deprecate __ASSEMBLY__ and switch the code base over to the predefined standard. Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417 Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 29 Jul, 2019 1 commit
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Ambroise Vincent authored
This change is needed for the platform to compile following the changes made in commits cbdc72b5 and 3e02c743 . Change-Id: I3468dd27f3b4f3095fb82f445d51cd8714311eb7 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 25 Jul, 2019 1 commit
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Ambroise Vincent authored
"result of '1 << 31' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=]" This is treated as an error since commit 93c690eb ("Enable -Wshift-overflow=2 to check for undefined shift behavior") Only the actual errors are being tackled by this patch. It is up to the platform to choose whether there needs to be further modifications to the code. Change-Id: I70860ae5f2a34d7c684bd491b76da50aa04f778e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 24 Jul, 2019 3 commits
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Julius Werner authored
The Rockchip platform is a prime candidate for switching to the new bl31_params_parse_helper(), so switch it over. This will allow BL2 implementations on this platform to transparently switch over to the version 2 parameter structure. Change-Id: I540741d2425c93f66c8697ce749a351eb2b3a7e8 Signed-off-by: Julius Werner <jwerner@chromium.org>
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Julius Werner authored
This patch adds a new include/export/ directory meant for inclusion in third-party code. This is useful for cases where third-party code needs to interact with TF-A interfaces and data structures (such as a custom BL2-implementation like coreboot handing off to BL31). Directly including headers from the TF-A repository avoids having to duplicate all these definitions (and risk them going stale), but with the current header structure this is not possible because handoff API definitions are too deeply intertwined with other TF code/headers and chain-include other headers that will not be available in the other environment. The new approach aims to solve this by separating only the parts that are really needed into these special headers that are self-contained and will not chain-include other (non-export) headers. TF-A code should never include them directly but should instead always include the respective wrapper header, which will include the required prerequisites (like <stdint.h>) before including the export header. Third-party code can include the export headers via its own wrappers that make sure the necessary definitions are available in whatever way that environment can provide them. Change-Id: Ifd769320ba51371439a8e5dd5b79c2516c3b43ab Signed-off-by: Julius Werner <jwerner@chromium.org>
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Julius Werner authored
This patch changes all Rockchip platforms to use the new common BL aux parameter helpers. Since the parameter space is now cleanly split in generic and vendor-specific parameters and the COREBOOT_TABLE parameter is now generic, the parameter type number for that parameter has to change. Since it only affects coreboot which always builds TF as a submodule and includes its headers directly to get these constants, this should not cause any issues. In general, after this point, we should avoid changing already assigned parameter type numbers whenever possible. Change-Id: Ic99ddd1e91ff5e5fe212fa30c793a0b8394c9dad Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 11 Jul, 2019 1 commit
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Justin Chadwell authored
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: Ib7fc54e4141cc4f1952a18241bc18671b36e2168 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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- 09 Jul, 2019 1 commit
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XiaoDong Huang authored
px30 is a Quad-core soc and Cortex-a53 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system 6. power off system Change-Id: I73d55aa978096c078242be921abe0ddca9e8f67e Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
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- 28 Jun, 2019 1 commit
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Ambroise Vincent authored
The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 29 May, 2019 1 commit
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Heiko Stuebner authored
In the rockchip bl31 setup the __RO_START__ and __RO_END__ symbols are currently imported into special BL31_RO_* constants while the general code also imports them as BL_CODE_BASE and BL_CODE_END. So we can just use the general symbols and can drop the duplication. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: Ibf1b48ad80bed897247a1690a32711030479262d
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- 02 May, 2019 1 commit
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Christoph Müllner authored
All supported Rockchip SoCs (RK3288, RK3328, RK3368 and RK3399) have non-continuous memory areas in the linker script with a huge gap between them. This results in extremely padded binary images with a size of about 4 GiB. E.g. on the RK3399 we have the following memory areas (and base addresses): RAM (0x1000), SRAM (0xFF8C0000), and PMUSRAM (0xFF3B0000). Consumers of the TF-A project (e.g. coreboot or U-Boot) therefore use the ELF image instead, which has a size of a few hundred kBs. In order to prevent the generation of a huge and useless file, this patch disables the binary generation for all affected Rockchip SoCs. Signed-off-by: Christoph Müllner <christophm30@gmail.com> Change-Id: I4ac65bdf1e598c3e1a59507897d183aee9a36916
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- 01 May, 2019 3 commits
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Christoph Müllner authored
Currently the compile-time constant PLAT_RK_UART_BASE defines which UART is used as console device. E.g. on RK3399 it is set to UART2. That means, that a single bl31 image can not be used for two boards, which just differ on the UART console. This patch addresses this limitation by parsing the "stdout-path" property from the "chosen" node in the DTB. The expected property string is expected to have the form "serialN:XXX", with N being either 0, 1, 2, 3 or 4. When the property is found, it will be used to override PLAT_RK_UART_BASE. Tested on RK3399-Q7, with a stdout-path of "serial0:115200n8". Signed-off-by: Christoph Müllner <christophm30@gmail.com> Change-Id: Iafe1320e77ab006c121f8d52745d54cef68a48c7
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Christoph Müllner authored
params_setup.c provides the function params_early_setup, which takes care of parsing ATF parameters (bl31_plat_param array, fdt or coreboot table). As params_early_setup is defined as weak symbol in bl31_plat_setup.c, providing a platform-specific bl31_plat_setup implementation is optional. This patch adds the rockchip-common params_setup.c to the sources for RK3328. This streamlines the parameter handling for all supported rockchip SoCs. Signed-off-by: Christoph Müllner <christophm30@gmail.com> Change-Id: I071c03106114364ad2fc408e49cc791fe5b35925
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Christoph Müllner authored
In order to set the UART base during bootup in common code of plat/rockchip, we need to streamline the way the UART base addresses are defined and add the missing definitions and mappings. This patch does so by following the pattern UARTn_BASE, which is already in use on RK3399 and RK3328. The numbering itself is derived from the upstream Linux DTS files of the individual SoCs. Signed-off-by: Christoph Müllner <christophm30@gmail.com> Change-Id: I341a1996f4ceed5f82a2f6687d4dead9d7cc5c1f
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- 26 Apr, 2019 1 commit
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Heiko Stuebner authored
While mainline u-boot always expects to submit the devicetree as platform param, coreboot always uses the existing parameter structure. As libfdt is somewhat big, it makes sense to limit its inclusion to where necessary and thus only to non-coreboot builds. libfdt itself will get build in all cases, but only the non- coreboot build will actually reference and thus include it. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I4c5bc28405a14e6070917e48a526bfe77bab2fb7
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- 25 Apr, 2019 5 commits
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Heiko Stuebner authored
The rk3288 is a 4-core Cortex-A12 SoC and shares a lot of features with later SoCs. Working features are general non-secure mode (the gic needs special love for that), psci-based smp bringing cpu cores online and also taking them offline again, psci-based suspend (the simpler variant also included in the linux kernel, deeper suspend following later) and I was also already able to test HYP-mode and was able to boot a virtual kernel using kvm. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: Ibaaa583b2e78197591a91d254339706fe732476a
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Heiko Stuebner authored
There are a number or ARMv7 Rockchip SoCs that are very similar in their bringup routines to the existing arm64 SoCs, so there is quite a high commonality possible here. Things like virtualization also need psci and hyp-mode and instead of trying to cram this into bootloaders like u-boot, barebox or coreboot (all used in the field), re-use the existing infrastructure in TF-A for this (both Rockchip plat support and armv7 support in general). So add core support for aarch32 Rockchip SoCs, with actual soc support following in a separate patch. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I298453985b5d8434934fc0c742fda719e994ba0b
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Heiko Stuebner authored
The cpuson_entry_point and cpuson_flags are already declared in plat_private.h so there is no need to have it again declared in the local pmu.h, especially as it may cause conflicts when the other type changes. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I80ae0e23d22f67109ed96f8ac059973b6de2ce87
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Heiko Stuebner authored
Some older socs like the rk3288 do not have the necessary registers to check the wfi/wfe state of the cpu cores. Allow this case an "just" do an additional delay similar to how the Linux kernel handles smp right now. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I0f67af388b06b8bfb4a9bac411b4900ac266a77a
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Heiko Stuebner authored
The current code doing power-management from sram is highly arm64-specific so should live in a corresponding subdirectory and not in the common area. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I3b79ac26f70fd189d4d930faa6251439a644c5d9
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- 24 Apr, 2019 1 commit
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Christoph Müllner authored
GCC complains for quite some versions, when compiling the M0 firmware for Rockchip's rk3399 platform, about an invalid type of function 'main': warning: return type of 'main' is not 'int' [-Wmain] This patch addresses this, by renaming the function to 'm0_main'. Signed-off-by: Christoph Müllner <christophm30@gmail.com> Change-Id: I10887f2bda6bdb48c5017044c264139004f7c785
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- 14 Mar, 2019 1 commit
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Heiko Stuebner authored
The Rockchip ATF platform can be entered from both Coreboot and U-Boot. While Coreboot does submit the list of linked parameter structs as platform param, upstream u-boot actually always provides a pointer to a devicetree as parameter. This results in current ATF not running at all when started from U-Boot. To fix this, add a stub that checks if the parameter is a fdt so we can at least boot and not get stuck. Later on we can extend this with actual parsing of information from the devicetree. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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- 01 Feb, 2019 1 commit
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Antonio Nino Diaz authored
Also, update platform_def.h guidelines about includes in the porting guide. Change-Id: I1ae338c9dd3242b309f6d53687ba2cb755d488c3 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 28 Jan, 2019 1 commit
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Antonio Nino Diaz authored
After the removal of deprecated interfaces in TF 2.0 the migration to the new GIC driver interfaces was done incorrectly in rk3328 and rk3368: 2d6f1f01 ("rockchip: Migrate to new interfaces"). In the GICv2 driver it is mandated that all interrupts are Group 0 interrupts. This patch simply moves all Group 1 interrupts to Group 0. Change-Id: I224c0135603eb5b81bd512976361500c0d129a91 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 07 Dec, 2018 1 commit
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Julius Werner authored
This patch makes the build system link the console framework code by default, like it already does with other common libraries (e.g. cache helpers). This should not make a difference in practice since TF is linked with --gc-sections, so the linker will garbage collect all functions and data that are not referenced by any other code. Thus, if a platform doesn't want to include console code for size reasons and doesn't make any references to console functions, the code will not be included in the final binary. To avoid compatibility issues with older platform ports, only make this change for the MULTI_CONSOLE_API. Change-Id: I153a9dbe680d57aadb860d1c829759ba701130d3 Signed-off-by: Julius Werner <jwerner@chromium.org>
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