- 27 Apr, 2021 1 commit
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Aditya Angadi authored
Add board support for RD-N2 Cfg1 variant of RD-N2 platform. It is a variant of RD-N2 platform with a reduced interconnect mesh size (3x3) and core count (8-cores). Its platform variant id is 1. Change-Id: I34ad35c5a5c1e9b69a658fb92ed00e5bc5fe72f3 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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- 11 Feb, 2021 1 commit
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Vijayenthiran Subramaniam authored
Update TZC base address to align with the recent changes in the platform memory map. Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: I0d0ad528a2e236607c744979e1ddc5c6d426687a
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- 16 Dec, 2020 1 commit
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Vijayenthiran Subramaniam authored
RD-N2 platform has been updated to use six GIC ITS blocks. This results in change in base address of the GIC Redistributor to accomodate two new GIC ITS blocks. Update the base address of GICR to reflect the same. Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: I740a547328fb9a9f25d7a09c08e61bdbc8bf781c
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- 09 Dec, 2020 2 commits
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Aditya Angadi authored
Add the initial board support for RD-N2 platform. Change-Id: I8325885bf248dd92191d6fc92a2da91c23118f8c Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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Aditya Angadi authored
Upcoming RD platforms have deviations in various definitions of platform macros from that of the exisiting platforms. In preparation for adding support for those upcoming RD platforms, refactor the header file inclusion to allow newer platforms to use a different set of platform macros. Change-Id: Ic80283ddadafaa7f766f300652cb0d4e507efdb6 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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- 12 Mar, 2020 1 commit
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Aditya Angadi authored
Add CLCD, HDLCD, PCI and VIRTIO devices as source interfaces for TZC filter unit to enable DMA for these devices. Change-Id: Ifad2e56b18605311936e03cfcccda573cac7e60a Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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- 19 Feb, 2020 1 commit
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Suyash Pathak authored
A TZC400 controller is placed inline on DRAM channels and regulates the secure and non-secure accesses to both secure and non-secure regions of the DRAM memory. Configure each of the TZC controllers accordingly. Change-Id: I75f6d13591a7fe9e50ce15c793e35a8018041815 Signed-off-by: Suyash Pathak <suyash.pathak@arm.com>
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- 07 Feb, 2020 3 commits
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Aditya Angadi authored
Add the initial board support for RD-Daniel Config-M platform. Change-Id: I36df16c745bfe4bc817e275ad4722e5de57733cd Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com> Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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Vijayenthiran Subramaniam authored
In preparation for adding support for Reference Design platforms which have different base addresses for GIC Distributor or Redistributor, move GIC related base addresses to individual platform definition files. Change-Id: Iecf52b4392a30b86905e1cd047c0ff87d59d0191 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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Aditya Angadi authored
In order to allow the MHUv2 driver to be usable with multiple MHUv2 controllers, use the base address of the controller from the platform information instead of the MHUV2_BASE_ADDR macro. Change-Id: I4dbab87b929fb0568935e6c8b339ce67937f8cd1 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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- 10 Jan, 2020 1 commit
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Deepika Bhavnani authored
NOTE for platform integrators: API `plat_psci_stat_get_residency()` third argument `last_cpu_idx` is changed from "signed int" to the "unsigned int" type. Issue / Trouble points 1. cpu_idx is used as mix of `unsigned int` and `signed int` in code with typecasting at some places leading to coverity issues. 2. Underlying platform API's return cpu_idx as `unsigned int` and comparison is performed with platform specific defines `PLAFORM_xxx` which is not consistent Misra Rule 10.4: The value of a complex expression of integer type may only be cast to a type that is narrower and of the same signedness as the underlying type of the expression. Based on above points, cpu_idx is kept as `unsigned int` to match the API's and low-level functions and platform defines are updated where ever required Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Ib26fd16e420c35527204b126b9b91e8babcc3a5c
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- 01 Aug, 2019 1 commit
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Julius Werner authored
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__. All common C compilers pre-define the same macros to signal which architecture the code is being compiled for: __arm__ for AArch32 (or earlier versions) and __aarch64__ for AArch64. There's no need for TF-A to define its own custom macros for this. In order to unify code with the export headers (which use __aarch64__ to avoid another dependency), let's deprecate the AARCH32 and AARCH64 macros and switch the code base over to the pre-defined standard macro. (Since it is somewhat unintuitive that __arm__ only means AArch32, let's standardize on only using __aarch64__.) Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200 Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 26 Jun, 2019 1 commit
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Manoj Kumar authored
N1SDP platform supports RDIMMs with ECC capability. To use the ECC capability, the entire DDR memory space has to be zeroed out before enabling the ECC bits in DMC620. Zeroing out several gigabytes of memory from SCP is quite time consuming so functions are added that zeros out the DDR memory from application processor which is much faster compared to SCP. BL33 binary cannot be copied to DDR memory before enabling ECC so this is also done by TF-A from IOFPGA-DDR3 memory to main DDR4 memory after ECC is enabled. Original PLAT_PHY_ADDR_SPACE_SIZE was limited to 36-bits with which the entire DDR space cannot be accessed as DRAM2 starts in base 0x8080000000. So these macros are redefined for all ARM platforms. Change-Id: If09524fb65b421b7a368b1b9fc52c49f2ddb7846 Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
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- 13 Mar, 2019 1 commit
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Masahisa Kojima authored
MHU doorbell driver requires arm platform specific macro "PLAT_CSS_MHU_BASE". Rename it to "PLAT_MHUV2_BASE", so that platforms other than arm can use generic MHU doorbell driver. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 27 Nov, 2018 2 commits
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Chandni Cherukuri authored
For platforms with multi-threaded CPUs, the number of power domains supported would be more than the value currently defined by PLAT_MAX_PWR_LVL. So move the PLAT_MAX_PWR_LVL macro to platform specific code and let the platform define the number of power domain levels. Change-Id: I21c0682e62b397860b2999031a0c9c5ce0d28eed Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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Chandni Cherukuri authored
The CSS_SYSTEM_PWR_DMN_LVL macro that defines the system power domain level is fixed at ARM_PWR_LVL2 for all CSS platforms. However, the system power domain level can be different for CSS platforms that use multi-threaded CPUs. So, in preparation towards adding support for platforms that use multi-threaded CPUs, refactor the definition of CSS_SYSTEM_PWR_DMN_LVL such that CSS_SYSTEM_PWR_DMN_LVL is uniquely defined for each of the CSS platform. Change-Id: Ia837b13f6865e71da01780993c048b45b7f36d85 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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- 21 Nov, 2018 1 commit
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Vijayenthiran Subramaniam authored
Remove the platform common plat_arm_security_setup function to allow platform specific implementations of the security setup function implemented in the board directory of the platform. For use by secure software, configure region0 of DMC-620 trustzone controller to protect the upper 16MB of memory of the first DRAM block from non-secure accesses. Change-Id: I9a8c19656702c4fa4f6917b3655b692d443bb568 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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- 18 Oct, 2018 1 commit
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Chandni Cherukuri authored
In preparation of adding support for upcoming SGI platforms, macros common to all the SGI platforms are moved into sgi_base_platform_def.h file. Macros that are specific to sgi575 platform remain in the platform_def.h file. In addition to this, the platform_def.h file is moved to sgi575 board directory. Also the ENT_CPU_SOURCES has been renamed to SGI_CPU_SOURCES and moved from sgi-common.mk to board specific makefile platform.mk Change-Id: Iccdd9f070f4feea232b9fbf4fdcc0ef2e8eccbf2 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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