- 01 Aug, 2019 1 commit
-
-
Julius Werner authored
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__. All common C compilers predefine a macro called __ASSEMBLER__ when preprocessing a .S file. There is no reason for TF-A to define it's own __ASSEMBLY__ macro for this purpose instead. To unify code with the export headers (which use __ASSEMBLER__ to avoid one extra dependency), let's deprecate __ASSEMBLY__ and switch the code base over to the predefined standard. Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417 Signed-off-by: Julius Werner <jwerner@chromium.org>
-
- 09 Jul, 2019 1 commit
-
-
XiaoDong Huang authored
px30 is a Quad-core soc and Cortex-a53 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system 6. power off system Change-Id: I73d55aa978096c078242be921abe0ddca9e8f67e Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
-
- 25 Apr, 2019 1 commit
-
-
Heiko Stuebner authored
The current code doing power-management from sram is highly arm64-specific so should live in a corresponding subdirectory and not in the common area. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I3b79ac26f70fd189d4d930faa6251439a644c5d9
-
- 28 Sep, 2018 1 commit
-
-
Antonio Nino Diaz authored
- Migrate to new GIC interfaces. - Migrate to bl31_early_platform_setup2(). - Use bl31_warm_entrypoint() instead of psci_entrypoint(). - Use PLAT_VIRT_ADDR_SPACE_SIZE and PLAT_PHY_ADDR_SPACE_SIZE. - Update Makefile paths. - Remove references to removed build options. - Use private definition of bl31_params_t. Change-Id: I860341594b5c868b2fcaa59d23957ee718472ef1 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
-
- 11 Jul, 2018 1 commit
-
-
Roberto Vargas authored
These directives are only used when stabs debugging information is used, but we use ELF which uses DWARF debugging information. Clang assembler doesn't support these directives, and removing them makes the code more compatible with clang. Change-Id: I2803f22ebd24c0fe248e04ef1b17de9cec5f89c4 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
-
- 29 Aug, 2017 1 commit
-
-
Lin Huang authored
when logic power rail shutdown, CRU register will back to reset value, ddr use abpll as clock source when do suspend, we need to save and dpll value in pmusram, then set back these ddr clock back to dpll when dddr resume. Change-Id: I95dc0173649e8515859cfa46b40a606e0cc2fe3f Signed-off-by: Lin Huang <hl@rock-chips.com>
-
- 08 Jun, 2017 3 commits
-
-
Lin Huang authored
unlike rk3399 and rk3368, there are some rockchip 64bit SOC do not have CPUPD, and pmu_cpuson_entrypoint() is common function for rockchip platform, so we need to check wakeup cpu when resume. Change-Id: I6313e8a9d7c16b03e033414f0cb281646c2159ff Signed-off-by: Lin Huang <hl@rock-chips.com>
-
Lin Huang authored
with PMU_PERILP_PD_EN bit enable, the soc will shutdown cm0, crypto, dcf, imem(normal SRAM), dmac, bootrom, efuse_con, spi, i2c, uart, saradc, tsadc when suspend, we have M0 code need to run when suspend in normal SRAM, so we need to take care of that. Change-Id: I8c066637e5b81d4b1d53197450b9d592cbe00793 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
-
Lin Huang authored
the function pmu_cpuon_entrypoint() need to run in the pmusram, we just copy bin file to pmusram before, now we add pmusram section and link pmu_cpuon_entrypoint() to pmusram directly Change-Id: Iae31e4c01c480c8e6f565a8f588332b478efdb16 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
-
- 03 May, 2017 1 commit
-
-
dp-arm authored
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
-
- 24 Feb, 2017 1 commit
-
-
Xing Zheng authored
We used dcf do ddr frequency scaling, but we just include a dcf binary, it hard to maintain later, we have M0 compile flow in ATF, and M0 can also work for ddr frequency scaling, so let's use it. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
-
- 14 Dec, 2016 1 commit
-
-
Antonio Nino Diaz authored
Some files have incorrect copyright notices, this patch fixes all files with deviations from the standard notice. Change-Id: I66b73e78a50a235acb55f1e2ec2052a42c0570d2 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
-
- 24 Oct, 2016 1 commit
-
-
Caesar Wang authored
Add the common extra.ld.S and customized rk3399.ld.S to extend to more features for different platforms. For example, we can add SRAM section and specific address to load there if we need it, and the common bl31.ld.S not need to be modified. Therefore, we can remove the unused codes which copying explicitly from the function pmusram_prepare(). It looks like more clear. Change-Id: Ibffa2da5e8e3d1d2fca80085ebb296ceb967fce8 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
-
- 11 Aug, 2016 1 commit
-
-
Caesar Wang authored
Sometimes this will cause the long delay for suspend/resume. Since the 24M OCS will be turned off in power mode. Also, remove the ERROR_DEPRECATED config define. Change-Id: I78f21c35912c2250972e551695cdacc7bc4c020a
-
- 28 Jul, 2016 1 commit
-
-
Caesar Wang authored
1. Remove the AP_PWROFF in ATF, should configure it in kernel. 2. Save and restore the PWMs pin/regs for suspend/resume. 3. The pmusgrf reset-hold bits needs to be released. since the pmusgrf reset-hold bits needs to be held. 4. Configure the PMU power up/down cycles about delay 3ms. 5. With the MMIO register block as one big mapping. 6. Fix the build error with psci_entrypoint since PSCI lib updated. Fixes the commit 9ec78bdf ("rockchip: support the suspend/resume for rk3399"). Change-Id: I112806700bf433c87763aac23d22fa7e6a7f5264
-
- 04 May, 2016 1 commit
-
-
Caesar Wang authored
This patch adds to support the suspend/resume for rk3399 SoCs. Signed-off-by: Shengfei xu <xsf@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
-
- 05 Apr, 2016 1 commit
-
-
Tony Xie authored
This patch adds to support the RK3368 and RK3399 SoCs. RK3368/RK3399 is one of the Rockchip family SoCs, which is an multi-cores ARM SoCs. This patch adds support to boot the Trusted Firmware on RK3368/RK3399 SoCs, and adds support to boot secondary CPUs, enter/exit core power states for all CPUs in the slow/fast clusters. This is the initial version for rockchip SoCs.(RK3368/RK3399 and next SoCs) * Support arm gicv2 & gicv3. * Boot up multi-cores CPU. * Add generic CPU helper functions. * Support suspend/resume. * Add system_off & system_reset implementation. * Add delay timer platform implementation. * Support the new porting interface for the PSCI implementation. Change-Id: I704bb3532d65e8c70dbd99b512c5e6e440ea6f43 Signed-off-by: Tony Xie <tony.xie@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Shengfei xu <xsf@rock-chips.com>
-