GitLab

Introduce support for RSU that can be initiated through SMC calls.

Added features as below:
- RSU status
- RSU update
- RSU HPS notify
- RSU get sub-partition
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I78d5a07688e43da99f03d77dfd45ffb4a78f2e4c

This patch enables uboot's spl entrypoint to BL31 and also handles
secondary cpus state during cold boot.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib70ec91a3ad09a568cb66e7c1e23a2b3e460746c

Removes unused source code for BL2 and BL31 in platform.mk.
Clean-up unused header files, syntax fixes, and alphabetical
sorting post-refactoring
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ie5ea9b4d3abdb0187cddeb04d2fcfb51fbe5c4dd

Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.

Share platform_def header between both Agilex and Stratix10 and store
platform specific definitions in socfpga_plat_def.h
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d

Previous config blocks ATF runtime service communications with SDM mailbox
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ic97aa381d3ceb96395595ec192132859d626b8d1

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib2ad2068abdf0b204c5cb021ea919581adaca4ef

This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A
supports:
- PSCI calls to enable 4 CPU cores
- PSCI mailbox calls for FPGA reconfiguration
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>