- 17 Jun, 2021 1 commit
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Venkatesh Yadav Abbarapu authored
As there is constraint with the space for the release builds, remove some of the legacy code. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Change-Id: I5b8b16f34ed8e480f16ab1aeac80b85cdb391852
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- 31 May, 2021 1 commit
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Venkatesh Yadav Abbarapu authored
Add support for XCK26 silicon which is available on SOM board. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Change-Id: Ic98213328702903af8a79f487a2868f3e6d60338
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- 21 Apr, 2021 1 commit
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Rajan Vaja authored
Counter frequency for generic timer of Arm-A53 based Application Processing Unit(APU) is not configuring in case if First Stage Boot Loader(FSBL) does not initialize counter frequency. This happens when FSBL is running from Arm-R5 based Real-time Processing Unit(RPU). Because of that generic timer driver functionality is not working. So configure counter frequency during initialization. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: Icfccd59d7d2340fba25ebfb2ef6a813af4290896
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- 03 Mar, 2021 1 commit
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Venkatesh Yadav Abbarapu authored
Add support for ZU43DR, ZU46DR and ZU47DR to the list of zynqmp devices. The ZU43DR, ZU46DR and ZU47DR RFSoC silicon id values are 0x7d, 0x78 and 0x7f. Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@xilinx.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Change-Id: I566f707116d83475de7c87a6004ca96bf7bccebe
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- 24 Feb, 2021 1 commit
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Venkatesh Yadav Abbarapu authored
Removing the custom crash implementation and use plat/common/aarch64/crash_console_helpers.S. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Change-Id: I045d42eb62bcaf7d1e18fbe9ab9fb9470e800215
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- 09 Oct, 2020 1 commit
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Jimmy Brisson authored
And from crash_console_flush. We ignore the error information return by console_flush in _every_ place where we call it, and casting the return type to void does not work around the MISRA violation that this causes. Instead, we collect the error information from the driver (to avoid changing that API), and don't return it to the caller. Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
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- 07 Jan, 2020 3 commits
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Edgar E. Iglesias authored
Correct the syscnt frequency for ZynqMP QEMU to 65Mhz. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: Ie0137feb9b7e24ed4e5d6cbf81c58ac77bb69214
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Venkatesh Yadav Abbarapu authored
Add support for zu48dr and zu49dr to the list of zynqmp devices. The zu48dr and zu49dr are the new RFSoC silicons with id values of 0x7b and 0x7e. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I2978f16bb663853951ef8059bf0327f909447f34
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Siva Durga Prasad Paladugu authored
This patch adds new RFSoC device ZU39DR to zynqmp devices list Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I35735da9e7d7facbde44323c49eac1b714e4909d
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- 10 Sep, 2019 1 commit
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Jolly Shah authored
Common ipi_table needs to be initialized before using any IPI command (i.e send/receive). Move zynqmp ipi config table initialization from sip_svc_setup() to zynqmp_config_setup(). Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf5b Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
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- 01 Jul, 2019 1 commit
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Ambroise Vincent authored
This patch addds multi console interface for ZynqMP platform Change-Id: I508a61412df2b71d04bca6a1139c8f32cbd7dccd Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
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- 09 Jan, 2019 1 commit
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Jolly Shah authored
Move zynqmp_private.h to platform specific include directory. Also, rename it to plat_private.h instead of having platform name. So, it can be used to common source files which needs platform specific data. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 25 Oct, 2018 1 commit
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Antonio Nino Diaz authored
Non-Arm platforms shouldn't use Arm platform code. This patch copies the implementation of the functions in arm_helpers.S to zynqmp_helpers.S to remove this dependency of zynqmp on Arm platforms. Change-Id: Ia85f303c4c63bcf0ffa57c7f3ef9d88376729b6b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 04 Sep, 2018 1 commit
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Siva Durga Prasad Paladugu authored
This patch removes support for emulation platforms EP108 and Veloce. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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- 21 Jun, 2018 1 commit
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Siva Durga Prasad Paladugu authored
This patch reads the chipid registers directly instead of making pm call when running at BL32. User should ensure that these registers should always be accessed from APU in their system configuration. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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- 17 May, 2018 5 commits
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Siva Durga Prasad Paladugu authored
The vcu disable bit in efuse ipdisable register is valid only if PL powered up so, consider PL powerup status for determing EG/EV part. If PL is not powered up, display EG/EV as a part of string. The PL powerup status will be filled by pmufw based on PL PROGB status in the 9th bit of version field.This patch also used IPI to get this info from pmufw instead of directly accessing the registers. Accessing this info from pmufw using IPI fixes the issue of PMUFW access denied error for reading IPDISABLE register. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
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Siva Durga Prasad Paladugu authored
Xilinx now requires the PMU FW when using ATF, so it doesn't make sense to maintain checks for the PMU FW in ATF. This also means that cases where ATF came up before the PMU FW (such as on QEMU) ATF will now hang waiting for the PMU FW instead of aborting. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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Siva Durga Prasad Paladugu authored
Read ipdisable reg which needs to be used for cg/eg/ev device detection. ATF runs in EL3 that's why this read can be done directly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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Siva Durga Prasad Paladugu authored
Add new id codes for RFSoC's. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Siva Durga Prasad Paladugu authored
Read boot mode register using pm_mmio_read if pmu is present otherwise access it directly using mmio_read_32(). Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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- 26 Mar, 2018 1 commit
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Jonathan Wright authored
Ensure (where possible) that switch statements in plat comply with MISRA rules 16.1 - 16.7. Change-Id: Ie4a7d2fd10f6141c0cfb89317ea28a755391622f Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
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- 03 May, 2017 1 commit
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dp-arm authored
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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- 05 Dec, 2016 1 commit
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Jeenu Viswambharan authored
There are many instances in ARM Trusted Firmware where control is transferred to functions from which return isn't expected. Such jumps are made using 'bl' instruction to provide the callee with the location from which it was jumped to. Additionally, debuggers infer the caller by examining where 'lr' register points to. If a 'bl' of the nature described above falls at the end of an assembly function, 'lr' will be left pointing to a location outside of the function range. This misleads the debugger back trace. This patch defines a 'no_ret' macro to be used when jumping to functions from which return isn't expected. The macro ensures to use 'bl' instruction for the jump, and also, for debug builds, places a 'nop' instruction immediately thereafter (unless instructed otherwise) so as to leave 'lr' pointing within the function range. Change-Id: Ib34c69fc09197cfd57bc06e147cc8252910e01b0 Co-authored-by: Douglas Raillard <douglas.raillard@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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- 16 Nov, 2016 3 commits
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Soren Brinkmann authored
Use the PMUFW get_chipid call to obtain IDCODE and version register. Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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Soren Brinkmann authored
On ZynqMP the FSBL will configure the system counter. Hence, remove the initialization of the system counter with hardcoded values from the ATF and use the setup provided by the bootloader. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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Soren Brinkmann authored
The silicon ID does not change at runtime. Skip the IO access if the ID has been read before. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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- 13 Sep, 2016 2 commits
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Siva Durga Prasad Paladugu authored
Add support to provide silicon id to non-secure software through SMC. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> [ sb Move zynqmp_get_silicon_id outside of compile guards to avoid build errors. ] Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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Soren Brinkmann authored
Initialize the generic_delay_timer in the zynqmp port. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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- 25 May, 2016 1 commit
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Soren Brinkmann authored
The revision field may change between silicon revisions without changing the mapping to a part. This avoids errors like: ERROR: Incorrect XILINX IDCODE 0x14738093, maskid 0x4600093 NOTICE: ATF running on XCZUUNKN/EP108 v3/RTL5.1 at 0xfffe5000 on parts with a newer revision. Reported-by: Love Kumar <love.kumar@xilinx.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Alistair Francis <alistair.francis@xilinx.com> Tested-by: Love Kumar <love.kumar@xilinx.com>
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- 20 May, 2016 1 commit
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Antonio Nino Diaz authored
Replaced plat_get_syscnt_freq by plat_get_syscnt_freq2 on all upstream platforms. Change-Id: I3248f3f65a16dc5e9720012a05c35b9e3ba6abbe
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- 25 Apr, 2016 2 commits
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Soren Brinkmann authored
Provide a function to retrieve the bootmode. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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Soren Brinkmann authored
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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- 21 Apr, 2016 1 commit
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Yatharth Kochar authored
This patch moves the definition for `plat_get_syscnt_freq()` from arm_bl31_setup.c to arm_common.c. This could be useful in case a delay timer needs to be installed based on the generic timer in other BLs. This patch also modifies the return type for this function from `uint64_t` to `unsigned long long` within ARM and other platform files. Change-Id: Iccdfa811948e660d4fdcaae60ad1d700e4eda80d
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- 18 Apr, 2016 1 commit
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Soren Brinkmann authored
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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- 06 Apr, 2016 1 commit
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Soren Brinkmann authored
The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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