- 09 Aug, 2019 1 commit
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Heiko Stuebner authored
Rockchip platforms can be booted from either u-boot or coreboot. So far the Coreboot-console was initizalized from a coreboot data struct in the early_param2 callbacks and dt-based consoles with data from the rockchip_get_uart_* functions. But later code may also need this console information for example for special suspend handling. To make this easy follow a suggestion from Julius Werner and move the coreboot<->dt distinction into the rockchip_get_uart_* functions, thus making correct data about the used uart available to all Rockchip platform code at all times. This includes a new rockchip_get_uart_clock as well, because while the dt-platforms right now always just default the rate defined in a constant Coreboot provides its own field for the clock rate and we don't want to loose that information for the console init. Similarly the rk_uart_* variables should move into the non-Coreboot code, to prevent them from being marked as unused, which also requires the rk_get_uart_* functions to move below the actual dt-parsing. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I278d595d2aa6c6864187fc8979a9fbff9814feac
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- 05 Aug, 2019 1 commit
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Heiko Stuebner authored
A previous patch already allowed to configure the uart output from the devicetree, but on Rockchip platforms we also have the issue of different vendors using different baudrates for their uarts. For example, rk3399 has a default baudrate of 115200 which is true for ChromeOS-devices and boards from Theobroma-Systems, while all the boards using the vendor boot chain actually use a baudrate of 1500000. Similarly the newly added px30 has a default of said 1500000 but some boards may want to use the more widely used 115200. The devicetree stdout-path node already contains the desired baudrate, so add simple code to parse it from there and override the default, which stays unchanged. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I7412139c3df3073a1996eb508ec08642ec6af90d
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- 24 Jul, 2019 2 commits
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Julius Werner authored
The Rockchip platform is a prime candidate for switching to the new bl31_params_parse_helper(), so switch it over. This will allow BL2 implementations on this platform to transparently switch over to the version 2 parameter structure. Change-Id: I540741d2425c93f66c8697ce749a351eb2b3a7e8 Signed-off-by: Julius Werner <jwerner@chromium.org>
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Julius Werner authored
This patch changes all Rockchip platforms to use the new common BL aux parameter helpers. Since the parameter space is now cleanly split in generic and vendor-specific parameters and the COREBOOT_TABLE parameter is now generic, the parameter type number for that parameter has to change. Since it only affects coreboot which always builds TF as a submodule and includes its headers directly to get these constants, this should not cause any issues. In general, after this point, we should avoid changing already assigned parameter type numbers whenever possible. Change-Id: Ic99ddd1e91ff5e5fe212fa30c793a0b8394c9dad Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 01 May, 2019 1 commit
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Christoph Müllner authored
Currently the compile-time constant PLAT_RK_UART_BASE defines which UART is used as console device. E.g. on RK3399 it is set to UART2. That means, that a single bl31 image can not be used for two boards, which just differ on the UART console. This patch addresses this limitation by parsing the "stdout-path" property from the "chosen" node in the DTB. The expected property string is expected to have the form "serialN:XXX", with N being either 0, 1, 2, 3 or 4. When the property is found, it will be used to override PLAT_RK_UART_BASE. Tested on RK3399-Q7, with a stdout-path of "serial0:115200n8". Signed-off-by: Christoph Müllner <christophm30@gmail.com> Change-Id: Iafe1320e77ab006c121f8d52745d54cef68a48c7
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- 25 Apr, 2019 1 commit
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Heiko Stuebner authored
There are a number or ARMv7 Rockchip SoCs that are very similar in their bringup routines to the existing arm64 SoCs, so there is quite a high commonality possible here. Things like virtualization also need psci and hyp-mode and instead of trying to cram this into bootloaders like u-boot, barebox or coreboot (all used in the field), re-use the existing infrastructure in TF-A for this (both Rockchip plat support and armv7 support in general). So add core support for aarch32 Rockchip SoCs, with actual soc support following in a separate patch. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I298453985b5d8434934fc0c742fda719e994ba0b
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 10 Oct, 2018 1 commit
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John Tsichritzis authored
The "Secure" prefix (S-ELx) is valid only for S-EL0 and S-EL1 but is meaningless for EL3, since EL3 is always secure. Hence, the "S" prefix has been removed from wherever it was used as "S-EL3". Change-Id: Icdeac9506d763f9f83d7297c7113aec7b85e9dbe Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 28 Sep, 2018 1 commit
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Antonio Nino Diaz authored
- Migrate to new GIC interfaces. - Migrate to bl31_early_platform_setup2(). - Use bl31_warm_entrypoint() instead of psci_entrypoint(). - Use PLAT_VIRT_ADDR_SPACE_SIZE and PLAT_PHY_ADDR_SPACE_SIZE. - Update Makefile paths. - Remove references to removed build options. - Use private definition of bl31_params_t. Change-Id: I860341594b5c868b2fcaa59d23957ee718472ef1 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 27 Mar, 2018 1 commit
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Joel Hutton authored
Void pointers have been used to access linker symbols, by declaring an extern pointer, then taking the address of it. This limits symbols values to aligned pointer values. To remove this restriction an IMPORT_SYM macro has been introduced, which declares it as a char pointer and casts it to the required type. Change-Id: I89877fc3b13ed311817bb8ba79d4872b89bfd3b0 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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- 19 Jan, 2018 2 commits
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Julius Werner authored
This patch changes all Rockchip platforms to use the new MULTI_CONSOLE_API. The platform-specific plat_crash_console implementations are removed so that the platform can use the ones from the common platform code instead. Also change the registers used in plat_crash_print_regs. The existing use of x16 and x17 has always been illegal, since those registers are reserved for use by the linker as a temporary scratch registers in intra-procedure-call veneers and can never be expected to maintain their values across a function call. Change-Id: I8249424150be8d5543ed4af93b56756795a5288f Signed-off-by: Julius Werner <jwerner@chromium.org>
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Julius Werner authored
This patch changes all Rockchip platforms to initialize the serial console with information supplied by coreboot rather than hardcoded base address and divisor values if BL31 is run on top of coreboot. Moving the BL2-to-BL31 parameter parsing as early as possible to ensure that the console is available for all following code. Also update the Rockchip platform to use MULTI_CONSOLE_API. Change-Id: I670d350fa2f8b8133539f91ac14977ab47db60d9 Signed-off-by: Julius Werner <jwerner@chromium.org>
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- 14 Jul, 2017 1 commit
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Isla Mitchell authored
This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions to this change in order to retain header groupings and where there are headers within #if statements. Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
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- 08 Jun, 2017 1 commit
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Lin Huang authored
the function pmu_cpuon_entrypoint() need to run in the pmusram, we just copy bin file to pmusram before, now we add pmusram section and link pmu_cpuon_entrypoint() to pmusram directly Change-Id: Iae31e4c01c480c8e6f565a8f588332b478efdb16 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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- 03 May, 2017 1 commit
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dp-arm authored
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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- 25 Apr, 2017 1 commit
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tony.xie authored
rk3328 is a Quad-core soc and Cortex-a53 inside! This patch supports the following functions: 1、power up/off cpus 2、suspend/resume cpus 3、suspend/resume system 4、reset system 5、power off system Change-Id: I60687058d13912c6929293b06fed9c6bc72bdc84 Signed-off-by: tony.xie <tony.xie@rock-chips.com>
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- 18 Jan, 2017 1 commit
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Masahiro Yamada authored
We have lots of duplicated defines (and comment blocks too). Move them to include/plat/common/common_def.h. While we are here, suffix the end address with _END instead of _LIMIT. The _END is a better fit to indicate the linker-derived real end address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 24 Oct, 2016 1 commit
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Caesar Wang authored
Add the common extra.ld.S and customized rk3399.ld.S to extend to more features for different platforms. For example, we can add SRAM section and specific address to load there if we need it, and the common bl31.ld.S not need to be modified. Therefore, we can remove the unused codes which copying explicitly from the function pmusram_prepare(). It looks like more clear. Change-Id: Ibffa2da5e8e3d1d2fca80085ebb296ceb967fce8 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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- 27 May, 2016 1 commit
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Caesar Wang authored
We add plat parameter structs to support BL2 to pass variable-length, variable-type parameters to BL31. The parameters are structured as a link list. During bl31 setup time, we travse the list to process each parameter. throuth this way, we can get the reset or power off gpio parameter, and do hardware control in BL31. This structure also can pass other parameter to BL31 in future.
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- 20 May, 2016 1 commit
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Antonio Nino Diaz authored
Use the generic delay timer instead of having a specific platform file for configuring it. Change-Id: Ifa68b9c97cd96ae1190cee74d22d729af95e4537
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- 05 Apr, 2016 1 commit
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Tony Xie authored
This patch adds to support the RK3368 and RK3399 SoCs. RK3368/RK3399 is one of the Rockchip family SoCs, which is an multi-cores ARM SoCs. This patch adds support to boot the Trusted Firmware on RK3368/RK3399 SoCs, and adds support to boot secondary CPUs, enter/exit core power states for all CPUs in the slow/fast clusters. This is the initial version for rockchip SoCs.(RK3368/RK3399 and next SoCs) * Support arm gicv2 & gicv3. * Boot up multi-cores CPU. * Add generic CPU helper functions. * Support suspend/resume. * Add system_off & system_reset implementation. * Add delay timer platform implementation. * Support the new porting interface for the PSCI implementation. Change-Id: I704bb3532d65e8c70dbd99b512c5e6e440ea6f43 Signed-off-by: Tony Xie <tony.xie@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Shengfei xu <xsf@rock-chips.com>
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- 01 Apr, 2016 1 commit
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Jimmy Huang authored
BL31 usually handles confidential stuff, its memory must not be read/write accessible from non-secure world. This patch protects the BL31 memory range from non-secure read/write access. Change-Id: I442fb92b667bb2f9a62d471a90508b1ba4489911 Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
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- 09 Mar, 2016 1 commit
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Jimmy Huang authored
MT8173 platform code is incompatible with RESET_TO_BL31, add #error directive to prevent the case. We also move mt8173_def.h and plat_private.h to include directory, and remove some unnecessary code. Change-Id: I47b8d0a506820a4ea1fbe8c8fb0ec6c68d88feb5 Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
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- 26 Jan, 2016 1 commit
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Jimmy Huang authored
This patch enables dynamic clock management control to reduce power consumption in various components. Change-Id: I8f66d9b72c8b1d70169ffe46cc361b16a0dadb77 Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
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- 11 Aug, 2015 1 commit
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CC Ma authored
- Boot up 4 cores. - Add a generic UART driver. - Add generic CPU helper functions - Supoort suspend - Add system_off & system_reset implementation - Add crash console reporting implementation - Add get_sys_suspend_power_state() for PSCI 1.0 SYSTEM_SUSPEND - Add Mediatek SIP runtime service - Add delay timer platform implementation Change-Id: I44138249f115ee10b9cbd26fdbc2dd3af04d825f Signed-off-by: CC Ma <cc.ma@mediatek.com> Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
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