GitLab

Removed '__ASSEMBLY__' deprecated macro from TF-A code

Change-Id: I9082a568b695acb5b903f509db11c8672b62d9d0
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

And from crash_console_flush.

We ignore the error information return by console_flush in _every_
place where we call it, and casting the return type to void does not
work around the MISRA violation that this causes. Instead, we collect
the error information from the driver (to avoid changing that API), and
don't return it to the caller.

Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

Use common ehf file for generic frameworks like SDEI, RAS and
extend plat specific defines using 'PLAT_EHF_DESC'.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Change-Id: I8a8161c6030f8d226a8bdf0301e7fe6139f019a4

If the CPU doesn't run from BL31_BASE, the firmware needs to be
copied from load address to BL31_BASE during cold boot. The size
should be the actual size of the code, which is indicated by the
__RELA_END__ linker variable.

This patch updates the copy routine to use this variable as a
result.
Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: Ie3a48dd54cda1dc152204903d609da3117a0ced9

The the GIC CPU interface should be disabled after cpu off. The
Tegra power management code should mark the connected core as asleep
as part of the CPU off sequence.

This patch disables the GICC after CPU off as a result.
Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: Ib1a3d8903f5e6d55bd2ee0c16134dbe2562235ea

This patch moves the BL31_SIZE to the Tegra SoC specific
tegra_def.h. This helps newer platforms configure the size of
the memory available for BL31.
Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: I43c60b82fa7e43d5b05d87fbe7d673d729380d82

This patch sanity checks the power state type before use,
from the platform's PSCI handler.

Verified with TFTF Standard Test Suite.

Change-Id: Icd45faac6c023d4ce7f3597b698d01b91a218124
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The delay_timer driver for Tegra uses the CNTPS_TVAL_EL1 secure, physical,
decrementing timer as the source. The current logic incorrectly marks this
as an incrementing timer, by negating the timer value.

This patch fixes the anomaly and updates the driver to remove this logic.
Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: I60490bdcaf0b66bf4553a6de3f4e4e32109017f4

Tegra SoCs would like the flexibility to perform chip specific actions
before we complete cold boot. This patch introduces a platform specific
'runtime_setup' handler to provide that flexibility.

Change-Id: I13b2489f631f775cae6f92acf51a240cd036ef11
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>

The SVE CPU extension library reads the id_aa64pfr0_el1 register to
check if SVE is enabled. Tegra platforms disabled ENABLE_SVE_FOR_NS for
pre-8.2 platforms, but this flag can safely be enabled now that the
library can enable the feature at runtime.

This patch updates the makefile to remove "ENABLE_SVE_FOR_NS = 0"
as a result.

Change-Id: Ia2a89ac90644f8c0d39b41d321e04458ff6be6e1
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>

This patch removes the unused header from the Tegra194
platform files. As a result, the TSA MMIO would be
removed from the memory map too.

Change-Id: I2d38b3da7a119f5dfd6cfd429e481f4e6ad3481e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The driver initially contained the setup steps to help Tegra186
and Tegra194 SoCs. In order to support future SoCs and make sure
that the driver remains generic enough, some code should be moved
to SoC.

This patch creates a setup handler for a platform to implement its
initialization sequence.

Change-Id: I8bab7fd07f25e0457ead8e2d2713efe54782a59b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The stream ID security configuration settings shall be done by the
previous level bootloader. This change removes the same settings
from the Tegra194 platform code as a result.

Change-Id: Ia170ca4c2119db8f1d0251f1c193add006f81004
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

The stream ID override configuration is saved during System Suspend
as part MB1 bct. This change removes the same support from the Tegra194
platform code as a result.

Change-Id: I4c19dc0d8b29190908673fb5ed7ed892af8906ab
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

This patch adds prints to display the completion of System Suspend
programming sequence for Tegra platforms. The console needs to
be kept alive until the very end of the System Suspend sequence as
a result.

Change-Id: I8e0e2054a272665d0a067bb894dda1605a9d2eb7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

After enabling the strict checking mode, verify that
the strict mode has really been enabled by querying
the MCE.

If the mode is found to be disabled, the code should
assert.

Change-Id: I113ec8decb737f8208059a2a3ba3076fad77890e
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

The Memory controller expects the TZDRAM base value at 1MB granularity
and the current driver does not respect that limitation. This patch
fixes that anomaly.

Change-Id: I6b72270f331ba5081e19811df4a78623e457341a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

In order to make sure SMC call is within 25us, this patch reduces number of RAS
errors accessed to 8 at most for each SMC call and takes a input/output
parameter to specify in progress RAS error record index.

The measured SMC call latency is about 20us under Linux test kernel driver.

Change-Id: Ia1b57c8673e0193dc341a36af0b5c09fb48f965f
Signed-off-by: David Pu <dpu@nvidia.com>

The TEGRA_GICv2_SOURCES contains the list of GIC sources required
to compile the GICv2 support for platforms.

This patch includes the TEGRA_GICv2_SOURCES macro from individual
makefiles to allow future platforms to use suport for GICv3.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I429b1a0c7764ab370675f873a50cecda871110cb

This patch adds memory barriers to the trampoline code copying TZDRAM
contents to SysRAM during exit from System Suspend. These barriers
make sure that all the copies go through before we start executing in
SysRAM.

Reported by: Nathan Tuck <ntuck@nvidia.com>

Change-Id: I3fd2964086b6c0e044cc4165051a4801440db9cd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The Memory Controller provides a control register to check
if the video memory can be resized. The previous bootloader
might have locked this feature, which will be reflected by
this register.

This patch reads the control register before processing
a video memory resize request. An error code, -ENOTSUP,
is returned if the feature is locked.

Change-Id: Ia1d67f7a94aa15c6b18ff5c9b9b952e179596ae3
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

MMIO writes should verify that the writes actually went through.
Read the value back after the write operation, perform assert
if the read back value is not same as the write value.

Change-Id: Id2ceb014116f3aa6a9e86505ca1ae9911470a679
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

This patch removes the unused cortex_a53.h header file from
common Tegra files.

This change fixes the violation of CERTC Rule: DCL23.

Change-Id: Iaf7c34cc6323b78028258e188c00724c52afba85
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

During boot the platform enables dual execution for Xavier CPUs.
This patch reads back the ACTLR_ELx register to verify that the bit
is actually set. It asserts if the bit is not set.

Change-Id: I5ba9491ced86285d307b95efa647a427ff77c79e
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>

The firewall settings for the hardware resources are present in the
Security Configuration Registers. The firewall settings are programmed
by other software components and so must be verified for correctness
before touching the hardware resources they protect.

This patch reads the firewall settings during early boot and asserts
if the settings mismatch.

Change-Id: I53cc9aeadad32e54e460db0fa2c38e46bcc92066
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch introduces the following changes to enable
compilation for `SPD=spmd` command line option.

* compile plat_spmd_manifest.c
* compile libfdt source files

Verified with the `SPD=spmd` command line option for
Tegra194 platforms.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I7f57aa4f1756b19f78d87415bb80794417174bc8

This patch includes the following files from libc to
compile libfdt:

* memchr.c
* memcmp.c
* strrchr.c

The BUILD_PLAT macro is evaluated earlier to allow libfdt
installation to the right directory.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ie43fcf701dc051670e6372e21b3a84a6416c1735

libfdt does not support the -Wsign-compare compiler option
and the right patch will eventually be pushed upstream.

This patch disables the -Wsign-compare compiler option
to allow libfdt compilation for Tegra platforms until
the actual issue is fixed.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ib7a93946cad1ea9ec1b46751edb79a74c08ed0ac

This patch removes the unused interrupt mapping for AON_WDT
for all Tegra194 platforms.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I475a1e83f809c740e62464b5b4e93cb0a2e33d6b

The SMMU configuration can get corrupted or updated by
external clients during boot without our knowledge.

This patch introduces a "verify" function for the SMMU
driver, to check that the boot configuration settings are
intact.  Usually, this function should be called at the
end of the boot cycle.

This function only calls panic() on silicon platforms.

Change-Id: I2ab45a7f228781e71c73ba1f4ffc49353effe146
Signed-off-by: George Bauernschmidt <georgeb@nvidia.com>

TZDRAM setup is not required for all Tegra SoCs. The previous bootloader
can enable the TZDRAM fence due to architectural improvements in the
newer chips.

This patch moves the TZDRAM setup to early_boot handlers for SoCs to
handle this scenario.

Change-Id: I6481b4f848a4dadc20cb83852cd8e19a242b3a34
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch removes the deprecated 'plat_core_pos_by_mpidr' function
from the Tegra platform port.

Change-Id: I32e06cb7269e4fbfaf9ad6c26d0722201f982f9e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

The GICC interface exists only on the interrupt controllers following
the GICv2 specification.

This patch prints the GICC register contents from the platform's macro,
plat_crash_print_regs' only when TEGRA_GICC_BASE is defined. This
allows platforms using future versions of the GIC specification to
still use this macro.

Change-Id: Ia5762d0a1ae28c832664d69362a7776e46a22ad1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

SPE no longer requires the flush bit to be set to start transmitting
characters over the physical uart. Therefore, the flush bit is no
longer required when calling console_core_putc. However, flushing the
console still requires the flush bit.

This patch removes the flush bit from the mailbox messages in
console_core_putc to improve ACK latency.

Original change by: Mustafa Bilgen <mbilgen@nvidia.com>

Change-Id: I5b7d1f3ea69ea2ce308566dbaae222b04e4c373d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

This patch verifies that the binary image is compatible with
chip ID of the platform.

Change-Id: I28db221b4442aa8827a092faadf32f110d7c5cb4
Signed-off-by: kalyanic <kalyanic@nvidia.com>

This reverts commit e7d344de.
 This reverts the patch https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/5313 due to a timing issue with the merge.  The merge occurred at the same time as the additional comments and thusly were were not seen until the merge was done.  This reverts the change and additional patches from Alexei will follow to address the concerns expressed in the orignal patch.

Change-Id: Iae5f6403c93ac13ceeda29463883fcd4c437f2b7

Trace analysis of FVP_Base_AEMv8A model running in
Aarch32 mode with the build options listed below:
TRUSTED_BOARD_BOOT=1 GENERATE_COT=1
ARM_ROTPK_LOCATION=devel_ecdsa KEY_ALG=ecdsa
ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem
shows that when auth_signature() gets called
71.84% of CPU execution time is spent in memset() function
written in C using single byte write operations,
see lib\libc\memset.c.
This patch replaces C memset() implementation with assembler
version giving the following results:
- for Aarch32 in auth_signature() call memset() CPU time
reduced to 24.84%.
- Number of CPU instructions executed during TF-A
boot stage before start of BL33 in RELEASE builds:
----------------------------------------------
|  Arch   |     C      |  assembler |    %   |
----------------------------------------------
| Aarch32 | 2073275460 | 1487400003 | -28.25 |
| Aarch64 | 2056807158 | 1244898303 | -39.47 |
----------------------------------------------
The patch also replaces memset.c with aarch64/memset.S
in plat\nvidia\tegra\platform.mk.

Change-Id: Ifbf085a2f577a25491e2d28446ee95a4ac891597
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

This patch adds tegra_chipid_is_t194() function to check if it is a
Tegra 194 chip.

Change-Id: I6da6d3a2c9676b748931e42fde1b174cbcb4fd40
Signed-off-by: David Pu <dpu@nvidia.com>

This patch makes Tegra platform psci ops routines to static. These
routines are called by PSCI framework and no external linkage is
necessary. This patch also fixes MISRA C-2012 Rule 8.6 violations.

Change-Id: Idd2381809f76dc0fd578c1c92c0f8eea124f2e88
Signed-off-by: David Pu <dpu@nvidia.com>

This patch removes the unused TZRAM setup function from the memory
controller driver.

Change-Id: Ic16f21fb84c47df71be6ab3e1e286640daa39291
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>