1. 15 Oct, 2020 1 commit
  2. 07 Apr, 2020 1 commit
    • Julius Werner's avatar
      coreboot: Add memory range parsing · 579d1e90
      Julius Werner authored
      
      
      This patch adds code to parse memory range information passed by
      coreboot, and a simple helper to test whether a specific address belongs
      to a range. This may be useful for coreboot-using platforms that need to
      know information about the system's memory layout (e.g. to check whether
      an address passed in via SMC targets valid DRAM).
      Signed-off-by: default avatarJulius Werner <jwerner@chromium.org>
      Change-Id: I3bea326c426db27d1a8b7d6e17418e4850e884b4
      579d1e90
  3. 08 Nov, 2018 1 commit
    • Antonio Nino Diaz's avatar
      Standardise header guards across codebase · c3cf06f1
      Antonio Nino Diaz authored
      
      
      All identifiers, regardless of use, that start with two underscores are
      reserved. This means they can't be used in header guards.
      
      The style that this project is now to use the full name of the file in
      capital letters followed by 'H'. For example, for a file called
      "uart_example.h", the header guard is UART_EXAMPLE_H.
      
      The exceptions are files that are imported from other projects:
      
      - CryptoCell driver
      - dt-bindings folders
      - zlib headers
      
      Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      c3cf06f1
  4. 22 Aug, 2018 1 commit
  5. 19 Jan, 2018 1 commit
    • Julius Werner's avatar
      Add platform-independent coreboot support library · 3429c77a
      Julius Werner authored
      
      
      This patch adds the foundation for a platform-independent coreboot
      support library that can be shared by all platforms that boot BL31 from
      coreboot (acting as BL2). It adds code to parse the "coreboot table", a
      data structure that coreboot uses to communicate different kinds of
      information to later-stage firmware and certain OS drivers.
      
      As a first small use case for this information, allow platforms to
      access the serial console configuration used by coreboot, removing the
      need to hardcode base address and divisors and allowing Trusted Firmware
      to benefit from coreboot's user configuration (e.g. which UART to pick
      and which baud rate to use).
      
      Change-Id: I2bfb39cd2609ce6640b844ab68df6c9ae3f28e9e
      Signed-off-by: default avatarJulius Werner <jwerner@chromium.org>
      3429c77a