- 30 Jul, 2018 2 commits
-
-
Daniel Boulby authored
Set the function pointers in the console struct and the functions they point to to const since they only need to be defined when the console is being initialised and should not be changed after Change-Id: I0574307111e3ab2f13d1a4a74c3fa75532dfa4be Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
-
Antonio Nino Diaz authored
Fix violations of MISRA C-2012 Rules 10.1, 10.3 and 10.4. Change-Id: I13c6acda798c1666892f630f097a23e68748f9e4 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
-
- 24 Jul, 2018 5 commits
-
-
Yann Gautier authored
The DDR driver is under dual license, BSD and GPLv2. The configuration parameters are taken from device tree. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
-
Yann Gautier authored
If a PMIC companion chip is present on board, it has to be configured for regulators supplies. This check is done with board DT configuration. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Pascal Paillet <p.paillet@st.com>
-
Yann Gautier authored
The management of pinctrl nodes of device tree is also added. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
-
Yann Gautier authored
The clock driver is under dual license, BSD and GPLv2. The clock driver uses device tree, so a minimal support for this is added. The required files for driver and DTS files are in include/dt-bindings/. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
-
Yann Gautier authored
STM32MP1 is a microprocessor designed by STMicroelectronics, based on a dual Arm Cortex-A7. It is an Armv7-A platform, using dedicated code from TF-A. STM32MP1 uses BL2 compiled with BL2_AT_EL3. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Pascal Paillet <p.paillet@st.com>
-
- 18 Jul, 2018 6 commits
-
-
Konstantin Porotchkin authored
Add common Marvell ARMADA platform components. This patch also includes common components for Marvell ARMADA 8K platforms. Change-Id: I42192fdc6525a42e46b3ac2ad63c83db9bcbfeaf Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
-
Konstantin Porotchkin authored
Add i2c driver for A8K SoC family. Change-Id: I5932b2fce286d84fc3ad5a74c4c456001faa3196 Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
-
Konstantin Porotchkin authored
Add thermal driver for A8K SoC family. The termal unit data is used by Marvell DRAM initialization code for optimizing the memory controller configuration Change-Id: Iad92689fa6e4224a89d872e9aa015393abd9cf73 Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
-
Konstantin Porotchkin authored
Add LLC (L3) cache management drivers for Marvell SoCs AP806, AP807 and AP810 Change-Id: Ic70710f9bc5b6b48395d62212df7011e2fbb5894 Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
-
Konstantin Porotchkin authored
Add ModularChip and MCI drivers for A8K SoC family. ModularChip drivers include support for the internal building blocks of Marvell ARMADA SoCs - APN806, APN807 and CP110 Change-Id: I9559343788fa2e5eb47e6384a4a7d47408787c02 Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
-
Konstantin Porotchkin authored
Add address decoding unit drivers for Marvell SoCs. Address decoding flow and address translation units chart are located at docs/marvell/misc/mvebu-a8k-addr-map.txt Change-Id: Id6ce311fa1f4f112df3adfac5d20449f495f71ed Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
-
- 03 Jul, 2018 1 commit
-
-
Yann Gautier authored
This change is largely based on existing eMMC framework by Haojian Zhuang (@hzhuang1). The MMC framework supports both eMMC and SD card devices. It was written as a new framework since breaking few eMMC framework APIs. At card probe and after the reset to idle command (CMD0), a Send Interface Condition Command is sent (CMD8) to distinguish between eMMC and SD card devices. eMMC devices go through the same sequence as in the former eMMC framework. Else the framework uses commands dedicated to SD-cards for init or frequency switch. A structure is created to share info with the driver. It stores: - the MMC type (eMMC, SD or SD HC) - the device size - the max frequency supported by the device - the block size: 512 for eMMC and SD-HC and read from CSD structure for older SD-cards Restriction to align buffers on block size has been removed. Cache maintenance was removed and is expected to be done in the platform or device driver. The MMC framework includes some MISRA compliance coding style maybe not yet ported in the existing eMMC framework. Fixes ARM-software/tf-issues#597 Signed-off-by: Yann Gautier <yann.gautier@st.com>
-
- 19 Jun, 2018 1 commit
-
-
Antonio Nino Diaz authored
The old API is deprecated and will eventually be removed. Arm platforms now use the multi console driver for boot and runtime consoles. However, the crash console uses the direct console API because it doesn't need any memory access to work. This makes it more robust during crashes. The AArch32 port of the Trusted Firmware doesn't support this new API yet, so it is only enabled in AArch64 builds. Because of this, the common code must maintain compatibility with both systems. SP_MIN doesn't have to be updated because it's only used in AArch32 builds. The TSP is only used in AArch64, so it only needs to support the new API without keeping support for the old one. Special care must be taken because of PSCI_SYSTEM_SUSPEND. In Juno, this causes the UARTs to reset (except for the one used by the TSP). This means that they must be unregistered when suspending and re-registered when resuming. This wasn't a problem with the old driver because it just restarted the UART, and there were no problems associated with registering and unregistering consoles. The size reserved for BL2 has been increased. Change-Id: Icefd117dd1eb9c498921181a21318c2d2435c441 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
-
- 11 Jun, 2018 1 commit
-
-
Benjamin Fair authored
On TI platforms the UART is disabled by default and must be explicitly enabled using the MDR1 register. NOTE: The original definition of http://www.ti.com/lit/ds/symlink/pc16550d.pdf has no MDR register, but many TI SoCs implementing 16550 do have a quirky MDR register implemented. So, this should be enabled with TI_16550_MDR_QUIRK NOTE: In such implementation, the CSR register does not exist. Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>
-
- 17 May, 2018 1 commit
-
-
Daniel Boulby authored
In 'console_set_scope' and when registering a console, field 'flags' of 'console_t' is assigned a 32-bit value. However, when it is actually used, the functions perform 64-bit reads to access its value. This patch changes all 64-bit reads to 32-bit reads. Change-Id: I181349371409e60065335f078857946fa3c32dc1 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
-
- 15 May, 2018 1 commit
-
-
Antonio Nino Diaz authored
This reverts commit 2f18aa1f . It is causing some tests to fail. Until the cause is found and fixed, it is needed to remove this commit from master. Change-Id: Ic5ff7a841903a15613e00379e87cbbd8a0e85152 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
-
- 11 May, 2018 2 commits
-
-
Antonio Nino Diaz authored
The old API is deprecated and will eventually be removed. Arm platforms now use the multi console driver for boot and runtime consoles. However, the crash console uses the direct console API because it doesn't need any memory access to work. This makes it more robust during crashes. The AArch32 port of the Trusted Firmware doesn't support this new API yet, so it is only enabled in AArch64 builds. Because of this, the common code must maintain compatibility with both systems. SP_MIN doesn't have to be updated because it's only used in AArch32 builds. The TSP is only used in AArch64, so it only needs to support the new API without keeping support for the old one. Special care must be taken because of PSCI_SYSTEM_SUSPEND. In Juno, this causes the UARTs to reset (except for the one used by the TSP). This means that they must be unregistered when suspending and re-registered when resuming. This wasn't a problem with the old driver because it just restarted the UART, and there were no problems associated with registering and unregistering consoles. The size of BL31 has been increased in builds with SPM. Change-Id: Icefd117dd1eb9c498921181a21318c2d2435c441 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
-
Antonio Nino Diaz authored
In the multi console driver, allowing to register the same console more than once may result in an infinte loop when putc is called. If, for example, a boot message is trying to be printed, but the consoles in the loop in the linked list are runtime consoles, putc will iterate forever looking for a console that can print boot messages (or a NULL pointer that will never come). This loop in the linked list can occur after restoring the system from a system suspend. The boot console is registered during the cold boot in BL31, but the runtime console is registered even in the warm boot path. Consoles are always added to the start of the linked list when they are registered, so this it what should happen if they were actually different structures: console_list -> NULL console_list -> BOOT -> NULL console_list -> RUNTIME -> BOOT -> NULL console_list -> RUNTIME -> RUNTIME -> BOOT -> NULL In practice, the two runtime consoles are the same one, so they create this loop: console_list -> RUNTIME -. X -> BOOT -> NULL ^ | `----' This patch adds an assertion to detect this problem. The assertion will fail whenever the same structure tries to be registered while being on the list. In order to assert this, console_is_registered() has been implemented. It returns 1 if the specified console is registered, 0 if not. Change-Id: I922485e743775ca9bd1af9cbd491ddd360526a6d Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
-
- 13 Apr, 2018 2 commits
-
-
Roberto Vargas authored
Rule 8.4: A compatible declaration shall be visible when an object or function with external linkage is defined Fixed for: make DEBUG=1 PLAT=fvp SPD=tspd TRUSTED_BOARD_BOOT=1 \ GENERATE_COT=1 ARM_ROTPK_LOCATION=devel_rsa \ ROT_KEY=arm_rotprivk_rsa.pem MBEDTLS_DIR=mbedtls all Change-Id: Ie4cd6011b3e4fdcdd94ccb97a7e941f3b5b7aeb8 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
-
Roberto Vargas authored
Rule 8.3: All declarations of an object or function shall use the same names and type qualifiers Fixed for: make DEBUG=1 PLAT=fvp SPD=tspd TRUSTED_BOARD_BOOT=1 \ GENERATE_COT=1 ARM_ROTPK_LOCATION=devel_rsa \ ROT_KEY=arm_rotprivk_rsa.pem MBEDTLS_DIR=mbedtls all Change-Id: Ia34fe1ae1f142e89c9a6c19831e3daf4d28f5831 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
-
- 09 Apr, 2018 1 commit
-
-
Amit Daniel Kachhap authored
Some low end platforms using DMC500 memory controller do not have CCI(Cache Coherent Interconnect) interface and only have non-coherent system interface support. Hence this patch makes the system interface count configurable from the platforms. Change-Id: I6d54c90eb72fd18026c6470c1f7fd26c59dc4b9a Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
-
- 31 Mar, 2018 1 commit
-
-
Michalis Pappas authored
Use the console_pl011_core_* functions directly in the crash console callbacks. This bypasses the MULTI_CONSOLE_API for the crash console (UART1), but allows using the crash console before the C runtime has been initialized (eg to call ASM_ASSERT). This retains backwards compatibility with respect to functionality when the old API is used. Use the MULTI_CONSOLE_API to register UART0 as the boot and runtime console. Fixes ARM-software/tf-issues#572 Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
-
- 26 Mar, 2018 1 commit
-
-
Jeenu Viswambharan authored
- Interrupt configuration is a 2-bit field, so the field shift has to be double that of the bit number. - Interrupt configuration (level- or edge-trigger) is specified in the MSB of the field, not LSB. Fixes applied to both GICv2 and GICv3 drivers. Fixes ARM-software/tf-issues#570 Change-Id: Ia6ae6ed9ba9fb0e3eb0f921a833af48e365ba359 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
-
- 24 Mar, 2018 1 commit
-
-
Michalis Pappas authored
Add crash_console_init declaration to console.h Only enable MULTI_CONSOLE_API for AArch64 Fixes ARM-software/tf-issues#571 Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
-
- 01 Mar, 2018 2 commits
-
-
Dan Handley authored
Emit runtime warnings when intializing the GIC drivers using the deprecated method of defining integer interrupt arrays in the GIC driver data structures; interrupt_prop_t arrays should be used instead. This helps platforms detect that they have migration work to do. Previously, no warning was emitted in this case. This affects both the GICv2 and GICv3 drivers. Also use the __deprecated attribute to emit a build time warning if these deprecated fields are used. These warnings are suppressed in the GIC driver compatibility functions but will be visible if platforms use them. Change-Id: I6b6b8f6c3b4920c448b6dcb82fc18442cfdf6c7a Signed-off-by: Dan Handley <dan.handley@arm.com>
-
Dan Handley authored
For platforms that have not migrated to MULTI_CONSOLE_API == 1, there are a lot of confusing deprecated declaration warnings relating to use of console_init() and console_uninit(). Some of these relate to use by the generic code, not the platform code. These functions are not really deprecated but *removed* when MULTI_CONSOLE_API == 1. This patch consolidates these warnings into a single preprocessor warning. The __deprecated attribute is removed from the console_init() and console_uninit() declarations. For preprocessor warnings like this to not cause fatal build errors, this patch adds -Wno-error=cpp to the build flags when ERROR_DEPRECATED == 0. This option (and -Wno-error=deprecated-declarations) is now added to CPPFLAGS instead of TF_CFLAGS to ensure the build flags are used in the assembler as well as the compiler. This patch also disentangles the MULTI_CONSOLE_API and ERROR_DEPRECATED build flags by defaulting MULTI_CONSOLE_API to 0 instead of ERROR_DEPRECATED. This allows platforms that have not migrated to MULTI_CONSOLE_API to use ERROR_DEPRECATED == 1 to emit a more meaningful build error. Finally, this patch bans use of MULTI_CONSOLE_API == 1 and AARCH32, since the AArch32 console implementation does not support MULTI_CONSOLE_API == 1. Change-Id: If762165ddcb90c28aa7a4951aba70cb15c2b709c Signed-off-by: Dan Handley <dan.handley@arm.com>
-
- 28 Feb, 2018 2 commits
-
-
Roberto Vargas authored
Rule 8.3: All declarations of an object or function shall use the same names and type qualifiers. Fixed for: make DEBUG=1 PLAT=fvp LOG_LEVEL=50 all Change-Id: I48201c9ef022f6bd42ea8644529afce70f9b3f22 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
-
Roberto Vargas authored
Rule 8.3: All declarations of an object or function shall use the same names and type qualifiers. Change-Id: Iff384187c74a598a4e73f350a1893b60e9d16cec Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
-
- 24 Feb, 2018 1 commit
-
-
fengbaopeng authored
Hynix ufs has deviations on hi36xx platform which will result in ufs bursts transfer failures at a very low probability. To fix the problem, the Hynix device must set the register VS_DebugSaveConfigTime to 0x10, which will set time reference for SaveConfigTime is 250 ns. The time reference for SaveConfigTime is 40 ns by default. Signed-off-by: fengbaopeng <fengbaopeng@hisilicon.com>
-
- 19 Jan, 2018 4 commits
-
-
Julius Werner authored
coreboot supports an in-memory console to store firmware logs even when no serial console is available. It is widely supported by coreboot-compatible bootloaders (including SeaBIOS and GRUB) and can be read by the Linux kernel. This patch allows BL31 to add its own log messages to this console. The driver will be registered automatically if coreboot support is compiled in and detects the presence of a console buffer in the coreboot tables. Change-Id: I31254dfa0c2fdeb7454634134b5707b4b4154907 Signed-off-by: Julius Werner <jwerner@chromium.org>
-
Julius Werner authored
This patch updates the Cadence CDNS console driver to support the new console API. The driver will continue to support the old API as well by checking the MULTI_CONSOLE_API compile-time flag. Change-Id: I2ef8fb0d6ab72696997db1e0243a533499569d6b Signed-off-by: Julius Werner <jwerner@chromium.org>
-
Julius Werner authored
This patch updates the ARM PL011 console driver to support the new console API. The driver will continue to support the old API as well by checking the MULTI_CONSOLE_API compile-time flag. Change-Id: Ic34e4158addbb0c5fae500c9cff899c05a4f4206 Signed-off-by: Julius Werner <jwerner@chromium.org>
-
Julius Werner authored
This patch updates the TI 16550 console driver to support the new console API. The driver will continue to support the old API as well by checking the MULTI_CONSOLE_API compile-time flag. Change-Id: I60a44b7ba3c35c74561824c04b8dbe3e3039324c Signed-off-by: Julius Werner <jwerner@chromium.org>
-
- 17 Jan, 2018 1 commit
-
-
Qixiang Xu authored
Add some macros according to JEDEC Standard Embedded Multi-Media Card (eMMC) Electrical Standard (5.1)": Table 145 - Bus Mode Selection. Change-Id: Iaa45e0582653ef4290efd60d039f0bdc420eeb47 Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
-
- 12 Dec, 2017 1 commit
-
-
Julius Werner authored
This patch overhauls the console API to allow for multiple console instances of different drivers that are active at the same time. Instead of binding to well-known function names (like console_core_init), consoles now provide a register function (e.g. console_16550_register()) that will hook them into the list of active consoles. All console operations will be dispatched to all consoles currently in the list. The new API will be selected by the build-time option MULTI_CONSOLE_API, which defaults to ${ERROR_DEPRECATED} for now. The old console API code will be retained to stay backwards-compatible to older platforms, but should no longer be used for any newly added platforms and can hopefully be removed at some point in the future. The new console API is intended to be used for both normal (bootup) and crash use cases, freeing platforms of the need to set up the crash console separately. Consoles can be individually configured to be active active at boot (until first handoff to EL2), at runtime (after first handoff to EL2), and/or after a crash. Console drivers should set a sane default upon registration that can be overridden with the console_set_scope() call. Code to hook up the crash reporting mechanism to this framework will be added with a later patch. This patch only affects AArch64, but the new API could easily be ported to AArch32 as well if desired. Change-Id: I35c5aa2cb3f719cfddd15565eb13c7cde4162549 Signed-off-by: Julius Werner <jwerner@chromium.org>
-
- 21 Nov, 2017 1 commit
-
-
Qixiang Xu authored
The flag support the following values: - sha256 (default) - sha384 - sha512 Change-Id: I7a49d858c361e993949cf6ada0a86575c3291066 Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
-
- 13 Nov, 2017 2 commits
-
-
Jeenu Viswambharan authored
On GICv3 systems, as a side effect of adding provision to handle EL3 interrupts (unconditionally routing FIQs to EL3), pending Non-secure interrupts (signalled as FIQs) may preempt execution in lower Secure ELs [1]. This will inadvertently disrupt the semantics of Fast SMC (previously called Atomic SMC) calls. To retain semantics of Fast SMCs, the GIC PMR must be programmed to prevent Non-secure interrupts from preempting Secure execution. To that effect, two new functions in the Exception Handling Framework subscribe to events introduced in an earlier commit: - Upon 'cm_exited_normal_world', the Non-secure PMR is stashed, and the PMR is programmed to the highest Non-secure interrupt priority. - Upon 'cm_entering_normal_world', the previously stashed Non-secure PMR is restored. The above sequence however prevents Yielding SMCs from being preempted by Non-secure interrupts as intended. To facilitate this, the public API exc_allow_ns_preemption() is introduced that programs the PMR to the original Non-secure PMR value. Another API exc_is_ns_preemption_allowed() is also introduced to check if exc_allow_ns_preemption() had been called previously. API documentation to follow. [1] On GICv2 systems, this isn't a problem as, unlike GICv3, pending NS IRQs during Secure execution are signalled as IRQs, which aren't routed to EL3. Change-Id: Ief96b162b0067179b1012332cd991ee1b3051dd0 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
-
Jeenu Viswambharan authored
Acknowledging interrupt shall return a raw value from the interrupt controller in which the actual interrupt ID may be encoded. Add a platform API to extract the actual interrupt ID from the raw value obtained from interrupt controller. Document the new function. Also clarify the semantics of interrupt acknowledge. Change-Id: I818dad7be47661658b16f9807877d259eb127405 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
-