- 13 Aug, 2020 1 commit
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Olivier Deprez authored
Following f3ccf036 the INFO print in amu_enable is causing a lot of print outs on UART1 in DEBUG mode especially on PSCI test cases because CPU_ON or SUSPEND operations call: cm_prepare_el3_exit => enable_extensions_nonsecure => amu_enable. PSCI SUSPEND is also very frequent in linux boot cases causing test timeout failures. Signed-off-by:
Olivier Deprez <olivier.deprez@arm.com> Change-Id: I63581f8fa489d44b3b1d10af3b7f6fdf3af44720
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- 10 Aug, 2020 1 commit
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Alexei Fedorov authored
This patch fixes the bug when AMUv1 group1 counters was always assumed being implemented without checking for its presence which was causing exception otherwise. The AMU extension code was also modified as listed below: - Added detection of AMUv1 for ARMv8.6 - 'PLAT_AMU_GROUP1_NR_COUNTERS' build option is removed and number of group1 counters 'AMU_GROUP1_NR_COUNTERS' is now calculated based on 'AMU_GROUP1_COUNTERS_MASK' value - Added bit fields definitions and access functions for AMCFGR_EL0/AMCFGR and AMCGCR_EL0/AMCGCR registers - Unification of amu.c Aarch64 and Aarch32 source files - Bug fixes and TF-A coding style compliant changes. Change-Id: I14e407be62c3026ebc674ec7045e240ccb71e1fb Signed-off-by:Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 08 Aug, 2020 1 commit
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johpow01 authored
MISRA defect cleanup and general code cleanup in mem_region.c and semihosting.c. This task also called for cleanup of the ARM NOR flash driver but that was removed at some point since the Jira task was created. This patch fixes all MISRA defects in these files except for a few "Calling function "console_flush()" which returns error information without testing the error information." errors which can't really be avoided. Defects Fixed File Line Rule lib/semihosting/semihosting.c 70 MISRA C-2012 Rule 14.4 (required) lib/semihosting/semihosting.c 197 MISRA C-2012 Rule 14.3 (required) lib/semihosting/semihosting.c 210 MISRA C-2012 Rule 14.4 (required) lib/utils/mem_region.c 128 MISRA C-2012 Rule 12.1 (advisory) Signed-off-by:John Powell <john.powell@arm.com> Change-Id: I21a039d1cfccd6aa4301da09daec15e373305a80
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- 04 Aug, 2020 1 commit
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Grant Likely authored
If the user tries to change BUILD_BASE to put the build products outside the build tree the compile will fail due to hard coded assumptions that $BUILD_BASE is a relative path. Fix by using $(abspath $(BUILD_BASE)) to rationalize to an absolute path every time and remove the relative path assumptions. This patch also adds documentation that BUILD_BASE can be specified by the user. Signed-off-by:
Grant Likely <grant.likely@arm.com> Signed-off-by:
Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib1af874de658484aaffc672f30029b852d2489c8
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- 29 Jul, 2020 1 commit
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Alexei Fedorov authored
This patch fixes violation of Rules 2.1, 7.3, 10.1, 10.4, 12.1, 14.3, 14.4, 17.7, 20.9 reported by MISRA-2012 scan and adds braces for conditional statements according to the TF-A coding style. Change-Id: Ib2463601fb43d955c3d901102b6dceaaad6614f3 Signed-off-by:
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- 23 Jul, 2020 4 commits
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johpow01 authored
This reverts commit 11af40b6, reversing changes made to 2afcf1d4. This errata workaround did not work as intended so we are reverting this change. In the future, when the corrected workaround is published in an SDEN, we will push a new workaround. This is the patch being reverted: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4750 Signed-off-by:
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Alexei Fedorov authored
This patch makes optimisation of Aarch32 memcpy4() function. Change-Id: If9cdaa4a1224f88fb14df8a308a645344b6c4f1c Signed-off-by: -
Manish V Badarkhe authored
Updated the function 'set_fw_config_info' to make it generic by doing below changes: 1. Rename function name from 'set_fw_config_info' to 'set_config_info' 2. Take image_id as an argument so that this function can set any config information. Signed-off-by:Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Icf29e19d3e9996d8154d84dbbbc76712fab0f0c1
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Manish V Badarkhe authored
Update the data type of the member 'config_max_size' present in the structure 'dyn_cfg_dtb_info_t' to uint32_t. This change is being done so that dyn_cfg_dtb_info_t and image_info structure should use same data type for maximum size. Change-Id: I9b5927a47eb8351bbf3664b8b1e047ae1ae5a260 Signed-off-by:
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- 21 Jul, 2020 1 commit
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Alexei Fedorov authored
This patch adds support for Measured Boot driver functionality to FCONF library code. Change-Id: I81cdb06f1950f7e6e58f938a1b9c2f74f7cfdf88 Signed-off-by:
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- 27 Jun, 2020 1 commit
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Madhukar Pappireddy authored
This version corresponds to the following commit <7be250b> libfdt: Correct condition for reordering blocks Also, updated the Juno romlib jumptable with fdt APIs. Change-Id: Ib6d28c1aea81c2144a263958f0792cc4daea7a1f Signed-off-by:Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 25 Jun, 2020 3 commits
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johpow01 authored
Neoverse N1 erratum 1800710 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885747/f/Arm_Neoverse_N1_MP050_Software_Developer_Errata_Notice_v21.pdf Signed-off-by:
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johpow01 authored
Cortex A77 erratum 1800714 is a Cat B erratum, present in older revisions of the Cortex A77 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. Since this is the first errata workaround implemented for Cortex A77, this patch also adds the required cortex_a77_reset_func in the file lib/cpus/aarch64/cortex_a77.S. This errata is explained in this SDEN: https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf Signed-off-by:
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Manish V Badarkhe authored
Modified the code to do below changes: 1. Load tb_fw_config along with fw_config by BL1. 2. Populate fw_config device tree information in the BL1 to load tb_fw_config. 3. In BL2, populate fw_config information to retrieve the address of tb_fw_config and then tb_fw_config gets populated using retrieved address. 4. Avoid processing of configuration file in case of error value returned from "fw_config_load" function. 5. Updated entrypoint information for BL2 image so that it's arg0 should point to fw_config address. Signed-off-by:
Louis Mayencourt <louis.mayencourt@arm.com> Change-Id: Ife6f7b673a074e7f544ee3d1bda7645fd5b2886c
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- 24 Jun, 2020 5 commits
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Manish V Badarkhe authored
Updated 'fconf_load_config' function to return the error. Error from 'fconf_load_config" gets handled by BL1 in subsequent patches. Signed-off-by: -
Manish V Badarkhe authored
Modified the `fconf_load_config` function so that it can additionally support loading of tb_fw_config along with fw_config. Signed-off-by:
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Manish V Badarkhe authored
Cleaned up confused naming between TB_FW and FW_CONFIG. Signed-off-by:
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Manish V Badarkhe authored
Added support in fiptool to include fw_config image in FIP. Signed-off-by: -
Manish V Badarkhe authored
Moved BL2 configuration nodes from fw_config to newly created tb_fw_config device tree. fw_config device tree's main usage is to hold properties shared across all BLx images. An example is the "dtb-registry" node, which contains the information about the other device tree configurations (load-address, size). Also, Updated load-address of tb_fw_config which is now located after fw_config in SRAM. Signed-off-by:
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- 22 Jun, 2020 2 commits
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johpow01 authored
Cortex A76 erratum 1800710 is a Cat B erratum, present in older revisions of the Cortex A76 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by:
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johpow01 authored
Cortex A76 erratum 1791580 is a Cat B erratum present in earlier revisions of the Cortex A76. The workaround is to set a bit in the implementation defined CPUACTLR2 register, which forces atomic store operations to write-back memory to be performed in the L1 data cache. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by:
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- 12 Jun, 2020 2 commits
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Varun Wadekar authored
This patch adds a build config 'RAS_TRAP_LOWER_EL_ERR_ACCESS' to set SCR_EL3.TERR during CPU boot. This bit enables trapping RAS register accesses from EL1 or EL2 to EL3. RAS_TRAP_LOWER_EL_ERR_ACCESS is disabled by default. Signed-off-by:Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ifb0fb0afedea7dd2a29a0b0491a1161ecd241438
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David Pu authored
This patch adds all Tegra194 RAS nodes definitions and support to handle all uncorrectable RAS errors. Change-Id: I109b5a8dbca91d92752dc282c4ca30f273c475f9 Signed-off-by:
David Pu <dpu@nvidia.com> Signed-off-by:
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- 09 Jun, 2020 1 commit
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Varun Wadekar authored
The Denver CPUs implement support for PMUv3 for ARMv8.1 and expect the PMCR_EL0 to be saved in non-secure context. This patch disables cycle counter when event counting is prohibited immediately on entering the secure world to avoid leaking useful information about the PMU counters. The context saving code later saves the value of PMCR_EL0 to the non-secure world context. Verified with 'PMU Leakage' test suite. ******************************* Summary ******************************* > Test suite 'PMU Leakage' Passed ================================= Tests Skipped : 2 Tests Passed : 2 Tests Failed : 0 Tests Crashed : 0 Total tests : 4 ================================= Signed-off-by:
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- 08 Jun, 2020 1 commit
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Manish Pandey authored
Add support to generate certificate "sip-sp-cert" for Secure Partitions(SP) owned by Silicon provider(SiP). To avoid deviation from TBBR specification the support is only added for dualroot CoT and not for TBBR CoT. A single certificate file is generated containing hash of individual packages. Maximum 8 secure partitions are supported. Following new options added to cert_tool: --sip-sp-cert --> SiP owned Secure Partition Content Certificate --sp-pkg1 --> Secure Partition Package1 file --sp-pkg2 ..... --sp-pkg8 Trusted world key pair is used for signing. Going forward, this feature can be extended for Platfrom owned Partitions, if required. Signed-off-by:
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- 02 Jun, 2020 2 commits
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Jimmy Brisson authored
Enhanced Counter Virtualization, ECV, is an architecture extension introduced in ARMv8.6. This extension allows the hypervisor, at EL2, to setup self-synchronizing views of the timers for it's EL1 Guests. This patch pokes the control register to enable this extension when booting a hypervisor at EL2. Change-Id: I4e929ecdf400cea17eff1de5cf8704aa7e40973d Signed-off-by:Jimmy Brisson <jimmy.brisson@arm.com>
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Jimmy Brisson authored
The Fine Grained Traps (FGT) architecture extension was added to aarch64 in ARMv8.6. This extension primarily allows hypervisors, at EL2, to trap specific instructions in a more fine grained manner, with an enable bit for each instruction. This patch adds support for this extension by enabling the extension when booting an hypervisor at EL2. Change-Id: Idb9013ed118b6a1b7b76287237096de992ca4da3 Signed-off-by:
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- 01 Jun, 2020 2 commits
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Jimmy Brisson authored
Change-Id: I89b90cbdfc8f2aa898b4f3676a4764f060f8e138 Signed-off-by: -
Jimmy Brisson authored
This should allow git to easily track file moves Signed-off-by:
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- 26 May, 2020 1 commit
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Alexei Fedorov authored
This patch fixes wrong ID_AA64DFR0_EL1 register read instead of ID_AA64PFR0_EL1 to detect support for MPAM extension. It also implements get_mpam_version() function which returns MPAM version as: 0x00: None Armv8.0 or later; 0x01: v0.1 Armv8.4 or later; 0x10: v1.0 Armv8.2 or later; 0x11: v1.1 Armv8.4 or later; Change-Id: I31d776b1a1b60cb16e5e62296d70adb129d7b760 Reported-by:
Matteo Zini <matteozini96@gmail.com> Signed-off-by:
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- 19 May, 2020 2 commits
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johpow01 authored
This patch enables the v8.6 extension to add a delay before WFE traps are taken. A weak hook plat_arm_set_twedel_scr_el3 has been added in plat/common/aarch64/plat_common.c that disables this feature by default but platform-specific code can override it when needed. The only hook provided sets the TWED fields in SCR_EL3, there are similar fields in HCR_EL2, SCTLR_EL2, and SCTLR_EL1 to control WFE trap delays in lower ELs but these should be configured by code running at EL2 and/or EL1 depending on the platform configuration and is outside the scope of TF-A. Signed-off-by: -
Max Shvetsov authored
Removing FPEXC32_EL2 from the register save/restore routine for EL2 registers since it is already a part of save/restore routine for fpregs. Signed-off-by:Max Shvetsov <maksims.svecovs@arm.com> Change-Id: I5ed45fdbf7c8efa8dcfcd96586328d4f6b256bc4
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- 14 May, 2020 1 commit
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Manish V Badarkhe authored
During context switching from higher EL (EL2 or higher) to lower EL can cause incorrect translation in TLB due to speculative execution of AT instruction using out-of-context translation regime. Workaround is implemented as below during EL's (EL1 or EL2) "context_restore" operation: 1. Disable page table walk using SCTLR.M and TCR.EPD0 & EPD1 bits for EL1 or EL2 (stage1 and stage2 disabled) 2. Save all system registers except TCR and SCTLR (for EL1 and EL2) 3. Do memory barrier operation (isb) to ensure all system register writes are done. 4. Restore TCR and SCTLR registers (for EL1 and EL2) Errata details are available for various CPUs as below: Cortex-A76: 1165522 Cortex-A72: 1319367 Cortex-A57: 1319537 Cortex-A55: 1530923 Cortex-A53: 1530924 More details can be found in mail-chain: https://lists.trustedfirmware.org/pipermail/tf-a/2020-April/000445.html Currently, Workaround is implemented as build option which is default disabled. Signed-off-by:
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- 30 Apr, 2020 1 commit
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Louis Mayencourt authored
Dynamic configuration properties are fconf properties. Modify the compatible string from "arm,.." to "fconf,.." to reflect this. Signed-off-by:
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- 29 Apr, 2020 1 commit
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Andre Przywara authored
Our fdtw_read_cells() implementation goes to great lengths to sanity-check every parameter and result, but leaves a big hole open: The size of the storage the value pointer points at needs to match the number of cells given. This can't be easily checked at compile time, since we lose the size information by using a void pointer. Regardless the current usage of this function is somewhat wrong anyways, since we use it on single-element, fixed-length properties only, for which the DT binding specifies the size. Typically we use those functions dealing with a number of cells in DT context to deal with *dynamically* sized properties, which depend on other properties (#size-cells, #clock-cells, ...), to specify the number of cells needed. Another problem with the current implementation is the use of ambiguously sized types (uintptr_t, size_t) together with a certain expectation about their size. In general there is no relation between the length of a DT property and the bitness of the code that parses the DTB: AArch64 code could encounter 32-bit addresses (where the physical address space is limited to 4GB [1]), while AArch32 code could read 64-bit sized properties (/memory nodes on LPAE systems, [2]). To make this more clear, fix the potential issues and also align more with other DT users (Linux and U-Boot), introduce functions to explicitly read uint32 and uint64 properties. As the other DT consumers, we do this based on the generic "read array" function. Convert all users to use either of those two new functions, and make sure we never use a pointer to anything other than uint32_t or uint64_t variables directly. This reveals (and fixes) a bug in plat_spmd_manifest.c, where we write 4 bytes into a uint16_t variable (passed via a void pointer). Also we change the implementation of the function to better align with other libfdt users, by using the right types (fdt32_t) and common variable names (*prop, prop_names). [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi#n874 [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/ecx-2000.dts Change-Id: I718de960515117ac7a3331a1b177d2ec224a3890 Signed-off-by:
Andre Przywara <andre.przywara@arm.com>
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- 07 Apr, 2020 2 commits
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Julius Werner authored
This patch adds code to parse memory range information passed by coreboot, and a simple helper to test whether a specific address belongs to a range. This may be useful for coreboot-using platforms that need to know information about the system's memory layout (e.g. to check whether an address passed in via SMC targets valid DRAM). Signed-off-by:Julius Werner <jwerner@chromium.org> Change-Id: I3bea326c426db27d1a8b7d6e17418e4850e884b4
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Masahiro Yamada authored
bakery_lock_normal.c uses the raw register accessor, read_sctlr(_el3) to check whether the dcache is enabled. Using is_dcache_enabled() is cleaner, and a good abstraction for the library code like this. A problem is is_dcache_enabled() is declared in the local header, lib/xlat_tables_v2/xlat_tables_private.h I searched for a good place to declare this helper. Moving it to arch_helpers.h, closed to cache operation helpers, looks good enough to me. I also changed the type of 'is_cached' to bool for consistency, and to avoid MISRA warnings. Change-Id: I9b016f67bc8eade25c316aa9c0db0fa4cd375b79 Signed-off-by:Masahiro Yamada <yamada.masahiro@socionext.com>
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- 03 Apr, 2020 2 commits
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Pramod Kumar authored
Present framework restricts platform to pass desired shareability attribute for normal memory region mapped in MMU. it defaults to inner shareability. There are platforms where memories (like SRAM) are not placed at snoopable region in advaned interconnect like CCN/CMN hence snoopable transaction is not possible to these memory. Though These memories could be mapped in MMU as MT_NON_CACHEABLE, data caches benefits won't be available. If these memories are mapped as cacheable with non-shareable attribute, when only one core is running like at boot time, MMU data cached could be used for faster execution. Hence adding support to pass the shareability attribute for memory regions. Signed-off-by:Pramod Kumar <pramod.kumar@broadcom.com> Change-Id: I678cb50120a28dae4aa9d1896e8faf1dd5cf1754
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Masahiro Yamada authored
Using get_current_el_maybe_constant() produces more optimized code because in most cases, we know the exception level at build-time. For example, BL31 runs at EL3, so unneeded code will be trimmed. [before] 0000000000000000 <is_dcache_enabled>: 0: d5384240 mrs x0, currentel 4: 53020c00 ubfx w0, w0, #2, #2 8: 7100041f cmp w0, #0x1 c: 54000081 b.ne 1c <is_dcache_enabled+0x1c> // b.any 10: d5381000 mrs x0, sctlr_el1 14: 53020800 ubfx w0, w0, #2, #1 18: d65f03c0 ret 1c: 7100081f cmp w0, #0x2 20: 54000061 b.ne 2c <is_dcache_enabled+0x2c> // b.any 24: d53c1000 mrs x0, sctlr_el2 28: 17fffffb b 14 <is_dcache_enabled+0x14> 2c: d53e1000 mrs x0, sctlr_el3 30: 17fffff9 b 14 <is_dcache_enabled+0x14> [after] 0000000000000000 <is_dcache_enabled>: 0: d53e1000 mrs x0, sctlr_el3 4: 53020800 ubfx w0, w0, #2, #1 8: d65f03c0 ret Change-Id: I3698fae9b517022ff9fbfd4cad3a320c6e137e10 Signed-off-by:
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- 02 Apr, 2020 1 commit
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Masahiro Yamada authored
If PLAT_RO_XLAT_TABLES is defined, the base xlat table goes to the .rodata section instead of .bss section. This causes a warning like: /tmp/ccswitLr.s: Assembler messages: /tmp/ccswitLr.s:297: Warning: setting incorrect section attributes for .rodata It is practically no problem, but I want to keep the build log clean. Put the base table into the "base_xlat_table" section to suppress the assembler warnings. The linker script determines its final destination; rodata section if PLAT_RO_XLAT_TABLES=1, or bss section otherwise. So, the result is the same. Change-Id: Ic85d1d2dddd9b5339289fc2378cbcb21dd7db02e Signed-off-by:
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