- 13 Apr, 2017 2 commits
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Pritesh Raithatha authored
This patch adds flexibility to the code to initialise multiple SMMU devices. The base address macro name has been changed to make it explicit that we support multiple SMMUs. Change-Id: Id4854fb010ebeb699512d79c769de24050c2ad69 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Pritesh Raithatha authored
This patch empowers the platforms to provide an array with the registers that must be saved/restored across System Suspend. Original-change-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 07 Apr, 2017 1 commit
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Pritesh Raithatha authored
This patch empowers the platforms to provide the settings (e.g. stream ID, security setting, transaction overrides) required by the Memory Controller driver. This allows the platforms to program the Memory Controller as per their needs and makes the driver scalable. Original-change-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 30 Mar, 2017 1 commit
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Varun Wadekar authored
This patch disables TCU prefetch for all the contexts in order to improve SMMU performance. Change-Id: I82ca49a0e396d9f064f5c62a5f00c4b2101d8459 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 23 Mar, 2017 1 commit
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Varun Wadekar authored
This patch adds support to save the BL31 state to the TZDRAM before entering system suspend. The TZRAM loses state during system suspend and so we need to copy the entire BL31 code to TZDRAM before entering the state. In order to restore the state on exiting system suspend, a new CPU reset handler is implemented which gets copied to TZDRAM during boot. TO keep things simple we use this same reset handler for booting secondary CPUs too. Change-Id: I770f799c255d22279b5cdb9b4d587d3a4c54fad7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 22 Mar, 2017 1 commit
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Varun Wadekar authored
This patch adds a device driver for the SMMU hardware block on Tegra186 SoCs. We use the generic ARM SMMU-500 IP block on Tegra186. The driver only supports saving the SMMU settings before entering system suspend. The MC driver and the NS world clients take care of programming their own settings. Change-Id: Iab5a90310ee10f6bc8745451ce50952ab3de7188 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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