- 01 Jun, 2020 1 commit
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Etienne Carriere authored
Changes stm32mp1 reset driver to API to add a timeout argument to stm32mp_reset_assert() and stm32mp_reset_deassert() and a return value. With a supplied timeout, the functions wait the target reset state is reached before returning. With a timeout of zero, the functions simply load target reset state in SoC interface and return without waiting. Helper functions stm32mp_reset_set() and stm32mp_reset_release() use a zero timeout and return without a return code. This change updates few stm32 drivers and plat/stm32mp1 blé_plat_setup.c accordingly without any functional change. functional change. Change-Id: Ia1a73a15125d3055fd8739c125b70bcb9562c27f Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 19 May, 2020 1 commit
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Manish V Badarkhe authored
CoT used for BL1 and BL2 are moved to tbbr_cot_bl1.c and tbbr_cot_bl2.c respectively. Common CoT used across BL1 and BL2 are moved to tbbr_cot_common.c. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I2252ac8a6960b3431bcaafdb3ea4fb2d01b79cf5
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- 11 May, 2020 6 commits
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Etienne Carriere authored
Adds missing terminal new line character '\n' to debug traces, fix format as index is an unsigned value and use present tense rather than past tense in the printed message. Change-Id: I88c06ef4d3a11d97ff8e96875a3dd0f58a3c98b6 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Enable few system clocks at related BL initialization. Change-Id: I12b35e8cdc128b993de4a1dc4c6e9d52624dd8d9 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Oscillators and PLLs are not gated on stm32mp_clk_enable/disable() calls. This change prevents functions to panic when called for such always-on clocks. Gating these clocks is out of the scope of this change. Change-Id: Ie730553dea480b529de942446176db9119587832 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Adds RTC clock to the list of the supported clocks. This allows stm32mp_clk_*() API functions to enable, disable and set and get rate for the clock RTC clock. Change-Id: I8efc3f00b1f22d1912f59d1846994e9e646d6614 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
The current implementation optimizes memory consumed by gateable clock table by storing bit mask and bit shift with 1 byte each. The issue is that register selector bit masks above the 7th LSBit cannot be stored. This change uses the shift info to shift the mask before it is used, allowing clock selector register bit fields to be spread on the 32 bits of the register as long as the mask fits in 8 contiguous bit at most. This change is needed to add the RTC clock to the gateable clocks table. Change-Id: I8a0fbcbf20ea383fb3d712f5064d2d307e44465d Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Oscillators, PLLs and some system clocks can be related straight to a parent clock. Prior this change were only oscillators and few clocks supported by this look up. This changes adds PLLs and other system clocks. This enables for flexible use of clock tree exploration when computing a clock frequency value. Change-Id: I15ec98023a7095e3120a6954de59a4799d92c66b Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 05 May, 2020 1 commit
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Andre Przywara authored
The STM32 platform port parse DT nodes to find base address to peripherals. It does this by using its own implementation, even though this functionality is generic and actually widely useful outside of the STM32 code. Re-implement fdt_get_reg_props_by_name() on top of the newly introduced fdt_get_reg_props_by_index() function, and move it to fdt_wrapper.c. This is removes the assumption that #address-cells and #size-cells are always one. Change-Id: I6d584930262c732b6e0356d98aea50b2654f789d Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 29 Apr, 2020 1 commit
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Andre Przywara authored
The STM32 platform code uses its own set of FDT helper functions, although some of them are fairly generic. Remove the implementation of fdt_read_uint32_default() and implement it on top of the newly introduced fdt_read_uint32() function, then convert all users over. This also fixes two callers, which were slightly abusing the "default" semantic. Change-Id: I570533362b4846e58dd797a92347de3e0e5abb75 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 28 Apr, 2020 1 commit
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Andre Przywara authored
The device tree parsing code for the STM32 platform is using its own FDT helper functions, some of them being rather generic. In particular the existing fdt_read_uint32_array() implementation is now almost identical to the new generic code in fdt_wrappers.c, so we can remove the ST specific version and adjust the existing callers. Compared to the original ST implementation the new version takes a pointer to the DTB as the first argument, and also swaps the order of the number of cells and the pointer. Change-Id: Id06b0f1ba4db1ad1f733be40e82c34f46638551a Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 07 Apr, 2020 3 commits
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Alexei Fedorov authored
To support compatibility with previous GICv3 driver version this patch: - restores original API for gicr_read_ipriority() and gicr_wrtite_ipriority() functions; - adds accessor functions for GICR_XXX0,1 registers, e.g. GICR_IGROUPR0, GICR_ICFGR0, GICR_ICFGR1, etc. Change-Id: I796a312a61665ff384e3d9de2f4b3c60f700b43b Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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Vijayenthiran Subramaniam authored
GIC-Clayton supports multichip operation mode which allows it to connect upto 16 other GIC-Clayton instances. GIC-Clayton's multichip programming and operation remains same as GIC-600 with a minor change in the SPI_BLOCKS and SPI_BLOCK_MIN shifts to accommodate additional SPI ranges. So identify if the GIC v4 extension is enabled by the platform makefile and appropriately select the SPI_BLOCKS and SPI_BLOCK_MIN shifts. Change-Id: I95fd80ef16af6c7ca09e2335539187b133052d41 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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Alexei Fedorov authored
This patch adds support for GICv4 extension. New `GIC_ENABLE_V4_EXTN` option passed to gicv3.mk makefile was added, and enables GICv4 related changes when set to 1. This option defaults to 0. Change-Id: I30ebe1b7a98d3a54863900f37eda4589c707a288 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 06 Apr, 2020 1 commit
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Alexei Fedorov authored
This patch provides support for GICv3.1 extended PPI and SPI range. The option is enabled by setting to 1 and passing `GIC_EXT_INTID` build flag to gicv3.mk makefile. This option defaults to 0 with no extended range support. Change-Id: I7d09086fe22ea531c5df51a8a1efd8928458d394 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 03 Apr, 2020 5 commits
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Sheetal Tigadoli authored
Add SPI Nor flash support Change-Id: I0cde3fdb4dcad5bcaf445b3bb48e279332bd28af Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
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Sheetal Tigadoli authored
Add iproc spi driver Change-Id: I652efab1efd9c487974dae9cb9d98b9b8e3759c4 Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
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Sheetal Tigadoli authored
Add emmc driver for Broadcom platforms Change-Id: I126a6dfccd41062cb0b856f2c2fb1f724730b95e Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
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Sheetal Tigadoli authored
Change-Id: Icfef5b6923dc292e637001045a334c499d346fe9 Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
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Sheetal Tigadoli authored
Change-Id: I5daa3f2b4b9d85cb857547a588571a9aa8ad05c2 Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
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- 01 Apr, 2020 2 commits
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Gilad Ben-Yossef authored
Add Crypto 713 support as crypto module and NVM counter provider. As files under include/drivers/arm/cryptocell/713/ are copied verbatim from the CryptoCell SBROM lib project they are filtered from checkpatch coding style check. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Change-Id: I7c361772f00ca7d96481f81ac6cbb2704467e52c
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Scott Branden authored
Add support to retrieve plat_toc_flags value from FIP header flags. plat_toc_flags is for platform specific use. It is stored in FIP header by fiptool using --plat-toc-flags option. Change-Id: Ibadd91b4f28e6503f4426e4efd404bbe512ad124 Signed-off-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
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- 30 Mar, 2020 1 commit
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Alexei Fedorov authored
This patch moves all GICv3 driver files into new added 'gicv3.mk' makefile for the benefit of the generic driver which can evolve in the future without affecting platforms. The patch adds GICv3 driver configuration flags 'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and 'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in 'GICv3 driver options' section of 'build-option.rst' document. NOTE: Platforms with GICv3 driver need to be modified to include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles. Change-Id: If055f6770ff20f5dee5a3c99ae7ced7cdcac5c44 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 26 Mar, 2020 1 commit
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Yann Gautier authored
A speculative accesses to DDR could be done whereas it was not reachable and could lead to bus stall. To correct this the dynamic mapping in MMU is used. A first mapping is done for DDR tests with MT_NON_CACHEABLE attribute, once DDR access is setup. It is then unmapped and a new mapping DDR is done with cacheable attribute (through MT_MEMORY) to speed-up BL33 (or OP-TEE) load. The disabling of cache during DDR tests is also removed, as now useless. A call to new functions stm32mp_{,un}map_ddr_non_cacheable() is done instead. PLAT_XLAT_TABLES_DYNAMIC is activated globally as used in BL2 and BL32. BL33 max size is also updated to take into account the secure and shared memory areas. Those are used in OP-TEE case. Change-Id: I22c48b4a48255ee264991c34ecbb15bfe87e67c3 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 25 Mar, 2020 1 commit
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Alexei Fedorov authored
This patch provides support for measured boot by adding calculation of BL2 image hash in BL1 and writing these data in TB_FW_CONFIG DTB. Change-Id: Ic074a7ed19b14956719c271c805b35d147b7cec1 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 23 Mar, 2020 3 commits
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Yann Gautier authored
This issue was found with cppcheck in our downstream code: [drivers/st/io/io_stm32image.c:234] -> [drivers/st/io/io_stm32image.c:244]: (warning) Either the condition 'buffer!=0U' is redundant or there is possible null pointer dereference: local_buffer. Change-Id: Ieb615b7e485dc93bbeeed4cd8bf845eb84c14ac9 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
The variable is wrongly set to 0L, whereas it is an unsigned int, it should then be 0U. Change-Id: I0b164c0ea598ec8a503f1693da2f3789f59da238 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Yann Gautier authored
Sparse issue: drivers/st/spi/stm32_qspi.c:445:5: warning: symbol 'stm32_qspi_init' was not declared. Should it be static? Cppcheck issue: [drivers/st/spi/stm32_qspi.c:175] -> [drivers/st/spi/stm32_qspi.c:187]: (style) Variable 'len' is reassigned a value before the old one has been used. [drivers/st/spi/stm32_qspi.c:178]: (style) The scope of the variable 'timeout' can be reduced. Change-Id: I575fb50766355a6717cbd193fc4a80ff1923014c Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 17 Mar, 2020 1 commit
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Andre Przywara authored
There is really no reason to use and pass around a struct when its only member is the (fixed) base address. Remove the struct and just use the base address on its own inside the GPIO driver. Then set the base address automatically. This simplifies GPIO setup for users, which now don't need to deal with zeroing a struct and setting the base address anymore. Change-Id: I3060f7859e3f8ef9a24cc8fb38307b5da943f127 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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- 10 Mar, 2020 1 commit
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Alexei Fedorov authored
This patch provides separation of GICD, GICR accessor functions and adds new macros for GICv3 registers access as a preparation for GICv3.1 and GICv4 support. NOTE: Platforms need to modify to include both 'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the single helper file previously. Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 08 Mar, 2020 1 commit
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Madhukar Pappireddy authored
Include x509.h header file explicitly. Update docs. Change-Id: If2e52c2cd3056654406b7b6779b67eea5cc04a48 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 06 Mar, 2020 2 commits
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Sumit Garg authored
TBBR spec advocates for optional encryption of firmwares (see optional requirement: R060_TBBR_FUNCTION). So add an IO abstaction layer to support firmware decryption that can be stacked above any underlying IO/ packaging layer like FIP etc. It aims to provide a framework to load any encrypted IO payload. Also, add plat_get_enc_key_info() to be implemented in a platform specific manner as handling of encryption key may vary from one platform to another. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I9892e0ddf00ebecb8981301dbfa41ea23e078b03
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Sumit Garg authored
Add framework for autheticated decryption of data. Currently this patch optionally imports mbedtls library as a backend if build option "DECRYPTION_SUPPORT = aes_gcm" is set to perform authenticated decryption using AES-GCM algorithm. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I2966f0e79033151012bf4ffc66f484cd949e7271
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- 05 Mar, 2020 1 commit
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Manish Pandey authored
The cpu index was wrongly checked causing it to assert always. Since this code path is exercised only during TF test "NODE_HW_STAT", which queries Power state from SCP, this bug was not detected earlier. Change-Id: Ia25cef4c0aa23ed08092df39134937a2601c21ac Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
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- 25 Feb, 2020 6 commits
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location for the coreboot memory console. This removes the base member from the coreboot specific data structure, but keeps the struct console_cbmc_t and its size member. Change-Id: I7f1dffd41392ba3fe5c07090aea761a42313fb5b Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I7a23327394d142af4b293ea7ccd90b843c54587c Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I07a07677153d3671ced776671e4f107824d3df16 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I347849424782333149e5912a25cc0ab9d277a201 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I9f8b55414ab7965e431e3e86d182eabd511f32a4 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Andre Przywara authored
Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: Iea6ca26ff4903c33f0fad27fec96fdbabd4e0a91 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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