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  1. 04 Oct, 2020 5 commits
  3. 01 Oct, 2020 1 commit
  5. 29 Sep, 2020 1 commit
    • Andre Przywara's avatar
      drivers: arm: gicv3: Allow detecting number of cores · 79d89e3d
      Andre Przywara authored 
      

A GICv3 interrupt controller will be instantiated for a certain number
of cores. This will result in the respective number of GICR frames. The
last frame will have the "Last" bit set in its GICR_TYPER register.

For platforms with a topology unknown at build time (the Arm FPGAs, for
instance), we need to learn the number of used cores at runtime, to size
the GICR region in the devicetree accordingly.

Add a generic function that iterates over all GICR frames until it
encounters one with the "Last" bit set. It returns the number of cores
the GICv3 has been configured for.

Change-Id: I79f033c50dfc1c275aba7122725868811abcc4f8
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      79d89e3d
  7. 28 Sep, 2020 1 commit
  9. 24 Sep, 2020 7 commits
  11. 22 Sep, 2020 1 commit
  13. 14 Sep, 2020 1 commit
  15. 17 Aug, 2020 1 commit
    • Andre Przywara's avatar
      plat/allwinner: Only enable DRIVEVBUS if really needed · 93fa305c
      Andre Przywara authored 
      

The DRIVEVBUS power rail of the AXP803 PMIC is mostly used to supply
the USB bus power on micro USB sockets, when used in host mode. As this
is a dynamic operation, and mostly we want micro USB sockets to act in
client mode initially, BL31 should not actually enable this power line.
However, on some boards DRIVEVBUS is used to supply power to normal
USB-A sockets. Failing to activate this line there results in
non-functional USB in U-Boot on those boards.

For that reason we were enabling DRIVEVBUS so far, as it did not seem to
cause any harm to the other boards. However it turns out that on the
Pinephone (and other systems with a battery), actually enabling DRIVEVBUS
unconditionally causes serious problems (reboot loop).

To accommodate both use cases, without reverting to a build time option,
check the default OTG configuration in the devicetree. For boards with
USB-A sockets this is set to "host", on boards with micro-B sockets to
"otg". Depending on this setting, we either enable DRIVEVBUS or leave it
alone.

This fixes TF-A on the Pinephone and potentially other battery powered
devices.

Change-Id: Iec0e07f218b2b4393bf4e05c3386261f8ed19e9f
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      93fa305c
  17. 12 Aug, 2020 1 commit
    • Manish Pandey's avatar
      dualroot: add chain of trust for Platform owned SPs · 2947412d
      Manish Pandey authored 
      

For dualroot CoT there are two sets of SP certificates, one owned by
Silicon Provider(SiP) and other owned by Platform. Each certificate can
have a maximum of 4 SPs.

This patch reduces the number of SiP owned SPs from 8 to 4 and adds
the remaining 4 to Plat owned SP.
Plat owned SP certificate is signed using Platform RoT key and
protected against anti-rollback using the Non-trusted Non-volatile
counter.

Change-Id: Idc3ddd87d6d85a5506a7435f45a6ec17c4c50425
Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
      2947412d
  19. 11 Aug, 2020 1 commit
    • Stefan Chulski's avatar
      plat: marvell: ap807: implement workaround for errata-id 3033912 · 5e4c97d0
      Stefan Chulski authored 
      

ERRATA ID: RES-3033912 - Internal Address Space Init state causes
a hang upon accesses to [0xf070_0000, 0xf07f_ffff]
Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to
split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and
[0x80_0000, 0xff_ffff] that cause accesses to the segment of
[0xf070_0000, 0xf07f_ffff] to act as RAZWI. Reuse common
work-around code for both AP806 and AP807.

Change-Id: Ia91a4802d02917d1682faa0c81571093d1687d97
Signed-off-by: default avatarStefan Chulski <stefanc@marvell.com>
      5e4c97d0
  21. 31 Jul, 2020 1 commit
    • Manish Pandey's avatar
      tbbr/dualroot: rename SP package certificate file · 03a5225c
      Manish Pandey authored 
      

Currently only single signing domain is supported for SP packages but
there is plan to support dual signing domains if CoT is dualroot.

SP_CONTENT_CERT_ID is the certificate file which is currently generated
and signed with trusted world key which in-turn is derived from Silicon
provider RoT key.
To allow dual signing domain for SP packages, other certificate file
will be derived from Platform owned RoT key.

This patch renames "SP_CONTENT_CERT_ID" to "SIP_SP_CONTENT_CERT_ID" and
does other related changes.
Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
Change-Id: I0bc445a3ab257e2dac03faa64f46e36a9fed5e93
      03a5225c
  23. 29 Jul, 2020 1 commit
  25. 27 Jul, 2020 1 commit
  27. 21 Jul, 2020 2 commits
  29. 20 Jul, 2020 1 commit
    • Alexei Fedorov's avatar
      TF-A GICv2 driver: Introduce makefile · 1322dc94
      Alexei Fedorov authored 
      

This patch moves all GICv2 driver files into new added
'gicv2.mk' makefile for the benefit of the generic driver
which can evolve in the future without affecting platforms.

NOTE: Usage of 'drivers/arm/gic/common/gic_common.c' file
is now deprecated and platforms with GICv2 driver need to
be modified to include 'drivers/arm/gic/v2/gicv2.mk' in
their makefiles.

Change-Id: Ib10e71bdda0e5c7e80a049ddce2de1dd839602d1
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      1322dc94
  31. 16 Jul, 2020 1 commit
    • johpow01's avatar
      IO Driver Misra Cleanup · d471bd9c
      johpow01 authored 
      

This patch cleans up MISRA C violations in the IO driver files.  Some
things did not make sense to fix or would require sweeping changes
but the simple issues have been resolved.

Defects Fixed

File                        Line Rule
drivers/io/io_fip.c         39   MISRA C-2012 Rule 5.6 (required)
drivers/io/io_fip.c         52   MISRA C-2012 Rule 8.9 (advisory)
drivers/io/io_fip.c         60   MISRA C-2012 Rule 5.9 (advisory)
drivers/io/io_fip.c         285  MISRA C-2012 Rule 8.9 (advisory)
drivers/io/io_fip.c         336  MISRA C-2012 Rule 15.4 (advisory)
drivers/io/io_fip.c         340  MISRA C-2012 Rule 15.4 (advisory)
drivers/io/io_fip.c         342  MISRA C-2012 Rule 15.4 (advisory)
drivers/io/io_memmap.c      30   MISRA C-2012 Rule 5.6 (required)
drivers/io/io_memmap.c      32   MISRA C-2012 Rule 5.9 (advisory)
drivers/io/io_memmap.c      85   MISRA C-2012 Rule 11.8 (required)
drivers/io/io_semihosting.c 66   MISRA C-2012 Rule 11.8 (required)
drivers/io/io_storage.c     73   MISRA C-2012 Rule 5.9 (advisory)
drivers/io/io_storage.c     116  MISRA C-2012 Rule 13.4 (advisory)
Signed-off-by: default avatarJohn Powell <john.powell@arm.com>
Change-Id: Id9b1b2b684588d4eaab674ed4ed04f3950dd21f4
      d471bd9c
  33. 13 Jul, 2020 1 commit
  35. 11 Jul, 2020 1 commit
  37. 10 Jul, 2020 5 commits
  39. 09 Jul, 2020 1 commit
  41. 08 Jul, 2020 5 commits