- 29 Aug, 2019 1 commit
-
-
Artsem Artsemenka authored
Change-Id: I576ae161477f4a69336d15a7741e566bb103124a Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
-
- 01 Aug, 2019 1 commit
-
-
Louis Mayencourt authored
At the time of writting, GCC 8.3-2019.03 is the latest version available on developer.arm.com. Switch to bare-metal toolchain (arm-eabi-) for AArch32. This allows to have a finer control on the use of floating-point and SIMD instructions. Change-Id: I4438401405eae1e5f6d531b0162e8fa06f69135e Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
-
- 22 Jul, 2019 1 commit
-
-
Imre Kis authored
The features of the previously existing gentbl, genvar and genwrappers scripts were reimplemented in the romlib_generator.py Python script. This resulted in more readable and maintainable code and the script introduces additional features that help dependency handling in makefiles. The assembly templates were separated from the script logic and were collected in the 'templates' directory. The targets and their dependencies were reorganized in the makefile and the dependency handling of included index files is possible now. Incremental build is available in case of modifying the index files. Signed-off-by: Imre Kis <imre.kis@arm.com> Change-Id: I79f65fab9dc5c70d1f6fc8f57b2a3009bf842dc5
-
- 18 Jul, 2019 1 commit
-
-
Louis Mayencourt authored
Add uml sequence and class diagram to illustrate the behavior of the storage abstraction layer. Change-Id: I338262729f8034cc3d3eea1d0ce19cca973a91bb Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
-
- 17 Jul, 2019 1 commit
-
-
Hadi Asyrafi authored
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib2ad2068abdf0b204c5cb021ea919581adaca4ef
-
- 12 Jul, 2019 1 commit
-
-
Paul Beesley authored
Currently we have some pre-rendered versions of certain diagrams in SVG format. These diagrams have corresponding PlantUML source that can be rendered automatically as part of the documentation build, removing the need for any intermediate files. This patch adds the Sphinx "plantuml" extension, replaces references to the pre-rendered SVG files within the documents, and finally removes the SVG files and helper script. New requirements for building the docs are the "sphinxcontrib-plantuml" Python module (added to the pip requirements.txt file) and the Graphviz package (provides the "dot" binary) which is in the Ubuntu package repositories. Change-Id: I24b52ee40ff79676212ed7cff350294945f1b50d Signed-off-by: Paul Beesley <paul.beesley@arm.com>
-
- 10 Jul, 2019 2 commits
-
-
Balint Dobszay authored
Change-Id: I755e4c42242d9a052570fd1132ca3d937acadb13 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
-
John Tsichritzis authored
The project has been renamed from "Arm Trusted Firmware (ATF)" to "Trusted Firmware-A (TF-A)" long ago. A few references to the old project name that still remained in various places have now been removed. This change doesn't affect any platform files. Any "ATF" references inside platform files, still remain. Change-Id: Id97895faa5b1845e851d4d50f5750de7a55bf99e Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
-
- 09 Jul, 2019 2 commits
-
-
John Tsichritzis authored
Change-Id: Ic5aab23b549d0bf8e0f7053b46fd59243214aac1 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
-
XiaoDong Huang authored
px30 is a Quad-core soc and Cortex-a53 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system 6. power off system Change-Id: I73d55aa978096c078242be921abe0ddca9e8f67e Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
-
- 08 Jul, 2019 1 commit
-
-
John Tsichritzis authored
Change-Id: Ibdee91ad337ee362872924d93e82f5b5e47e63d9 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
-
- 02 Jul, 2019 9 commits
-
-
lauwal01 authored
Neoverse N1 erratum 1275112 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: If7fe55fe92e656fa6aea12327ab297f2e6119833 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
-
lauwal01 authored
Neoverse N1 erratum 1262888 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
-
lauwal01 authored
Neoverse N1 erratum 1262606 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
-
lauwal01 authored
Neoverse N1 erratum 1257314 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR3_EL1 system register, which prevents parallel execution of divide and square root instructions. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
-
lauwal01 authored
Neoverse N1 erratum 1220197 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUECTLR_EL1 system register, which disables write streaming to the L2. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
-
lauwal01 authored
Neoverse N1 erratum 1207823 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
-
lauwal01 authored
Neoverse N1 erratum 1165347 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
-
lauwal01 authored
Neoverse N1 erratum 1130799 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
-
lauwal01 authored
Neoverse N1 erratum 1073348 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which disables static prediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
-
- 01 Jul, 2019 1 commit
-
-
Soby Mathew authored
Credit to sam.ellis@arm.com for the input to create the list. Change-Id: Id70a8eddc5f2490811bebb278482c61950f10cce Signed-off-by: Soby Mathew <soby.mathew@arm.com>
-
- 24 Jun, 2019 1 commit
-
-
John Tsichritzis authored
Change-Id: Ifef4d634b4a34d23f42f61df5e326a1cc05d3844 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
-
- 22 Jun, 2019 1 commit
-
-
Peng Donglin authored
Signed-off-by: Peng Donglin <dolinux.peng@gmail.com> Change-Id: I459e7d056735222f6f34e275dbdaf9a389d193fc
-
- 17 Jun, 2019 1 commit
-
-
Yann Gautier authored
U-Boot should be compiled with stm32mp15_trusted_defconfig which is supported since tag v2019.07-rc1 with commit [1]. The creation of the U-Boot binary with stm32 header is done at U-Boot compilation step, it is no more required to call the extra command. [1] https://git.denx.de/?p=u-boot.git;a=commit;h=015289580f81 Change-Id: Ia875c22184785fc2e02ad07993a649069cd5ce34 Signed-off-by: Yann Gautier <yann.gautier@st.com>
-
- 12 Jun, 2019 1 commit
-
-
Ambroise Vincent authored
Reference security specific build options from the user guide. Change-Id: I0e1efbf47d914cf3c473104175c702ff1a80eb67 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
-
- 10 Jun, 2019 1 commit
-
-
John Tsichritzis authored
Also sort alphabetically the links at the bottom, a couple of them were not sorted. Change-Id: I49a1dbe9e56a36c5fdbace8e4c8b9a5270bc2984 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
-
- 06 Jun, 2019 2 commits
-
-
Andre Przywara authored
Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register, which will disable the load-bypass-store feature. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-
Ambroise Vincent authored
Change-Id: I0d9dbef7041fcf950bcafcdbbc17c72b4dea9e40 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
-
- 03 Jun, 2019 1 commit
-
-
John Tsichritzis authored
Change-Id: I41ce5323c33a81db13c5cc40de1ac4e221a10cd8 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
-
- 31 May, 2019 1 commit
-
-
John Tsichritzis authored
Change-Id: I5cf8c70a304bf5869cbeb12fa8d39171cff48ebd Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
-
- 30 May, 2019 2 commits
-
-
Paul Beesley authored
Automatic labelling of document titles is a prerequisite for converting the format of cross-document links. Sphinx will generate (via the enabled extension) a hidden link target for each document title and this can be referred to later, from another page, to link to the target. The plugin options being used require Sphinx >= 2.0.0 so a requirements.txt file has been added. This file is used with the pip package manager for Python so that the correct dependencies are installed. Change-Id: Ic2049db5804aa4a6447608ba4299de958ce0a87d Signed-off-by: Paul Beesley <paul.beesley@arm.com>
-
John Tsichritzis authored
Change-Id: Ib021c721652d96f6c06ea18741f19a72bba1d00f Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
-
- 28 May, 2019 2 commits
-
-
Ambroise Vincent authored
The workaround is added to the Cortex-A55 cpu specific file. The workaround is disabled by default and have to be explicitly enabled by the platform integrator. Change-Id: I3e6fd10df6444122a8ee7d08058946ff1cc912f8 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
-
John Tsichritzis authored
Change-Id: Ic09e74f22b43fba51ee17cd02b5e1dc5d8e0bb63 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
-
- 24 May, 2019 3 commits
-
-
Alexei Fedorov authored
This patch adds the functionality needed for platforms to provide Branch Target Identification (BTI) extension, introduced to AArch64 in Armv8.5-A by adding BTI instruction used to mark valid targets for indirect branches. The patch sets new GP bit [50] to the stage 1 Translation Table Block and Page entries to denote guarded EL3 code pages which will cause processor to trap instructions in protected pages trying to perform an indirect branch to any instruction other than BTI. BTI feature is selected by BRANCH_PROTECTION option which supersedes the previous ENABLE_PAUTH used for Armv8.3-A Pointer Authentication and is disabled by default. Enabling BTI requires compiler support and was tested with GCC versions 9.0.0, 9.0.1 and 10.0.0. The assembly macros and helpers are modified to accommodate the BTI instruction. This is an experimental feature. Note. The previous ENABLE_PAUTH build option to enable PAuth in EL3 is now made as an internal flag and BRANCH_PROTECTION flag should be used instead to enable Pointer Authentication. Note. USE_LIBROM=1 option is currently not supported. Change-Id: Ifaf4438609b16647dc79468b70cd1f47a623362e Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
-
John Tsichritzis authored
1) Fix links in "about" page 2) Put back the "contents" page with adjusted links Change-Id: Id09140b91df5cf0a275149801d05d8cfeeda1c6e Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
-
John Tsichritzis authored
1) Replace references to "Arm Trusted Firmware" with "TF-A" 2) Update issue tracker link Change-Id: I12d827d49f6cc34e46936d7f7ccf44e32b26a0bd Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
-
- 22 May, 2019 3 commits
-
-
Paul Beesley authored
The documentation contains plenty of notes and warnings. Enable special rendering of these blocks by converting the note prefix into a .. note:: annotation. Change-Id: I34e26ca6bf313d335672ab6c2645741900338822 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
-
Paul Beesley authored
- Make the list of contributors into an actual list - Use note syntax for the note - Remove the Individuals heading since there are none This file could be considered for removal as it is a legacy document, as its note explains. Change-Id: Idf984bc192af7a0ec367a6642ab99ccccf5df1a8 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
-
Paul Beesley authored
Change-Id: I679d1499376a524bef1cfc33df995b0a719b5ac8 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
-