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  1. 28 Jan, 2020 1 commit
  3. 19 Nov, 2019 1 commit
  5. 15 Nov, 2019 1 commit
    • Alexei Fedorov's avatar
      GIC-600: Fix power up sequence · 7a7fbb12
      Alexei Fedorov authored 
      

Arm's GIC-600 features a Power Register (GICR_PWRR),
which needs to be programmed to enable redistributor
operation. Section 3.6.1 in the GIC-600 TRM describes
the power-up and power-down sequence in pseudo code,
which deviates from the current TF-A implementation
in drivers/arm/gic/v3/gic600.c.
For powering on a redistributor, the pseudo code suggests
to loop over the whole sequence (check for transition,
write request bit) instead of just looping over the
ready bit read as TF-A does in gic600_pwr_on().
This patch fixes GIC-600 power up sequence according
to the TRM.

Change-Id: I445c480e96ba356b69a2d8e5308ffe6c0a97f45b
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      7a7fbb12
  7. 11 Nov, 2019 1 commit
  9. 26 Sep, 2019 1 commit
    • Madhukar Pappireddy's avatar
      GICv3: Enable multi socket GIC redistributor frame discovery · ec834925
      Madhukar Pappireddy authored 
      

This patch provides declaration and definition of new GICv3 driver
API: gicv3_rdistif_probe().This function delegates the responsibility
of discovering the corresponding Redistributor base frame to each CPU
itself. It is a modified version of gicv3_rdistif_base_addrs_probe()
and is executed by each CPU in the platform unlike the previous
approach in which only the Primary CPU did the discovery of all the
Redistributor frames for every CPU.

The flush operations as part of gicv3_driver_init() function are
made necessary even for platforms with WARMBOOT_ENABLE_DCACHE_EARLY
because the GICv3 driver data structure contents are accessed by CPU
with D-Cache turned off during power down operations.

Change-Id: I1833e81d3974b32a3e4a3df4766a33d070982268
Signed-off-by: default avatarMadhukar Pappireddy <madhukar.pappireddy@arm.com>
      ec834925
  11. 13 Sep, 2019 1 commit
  13. 01 Aug, 2019 1 commit
    • Julius Werner's avatar
      Switch AARCH32/AARCH64 to __aarch64__ · 402b3cf8
      Julius Werner authored 
      

NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.

All common C compilers pre-define the same macros to signal which
architecture the code is being compiled for: __arm__ for AArch32 (or
earlier versions) and __aarch64__ for AArch64. There's no need for TF-A
to define its own custom macros for this. In order to unify code with
the export headers (which use __aarch64__ to avoid another dependency),
let's deprecate the AARCH32 and AARCH64 macros and switch the code base
over to the pre-defined standard macro. (Since it is somewhat
unintuitive that __arm__ only means AArch32, let's standardize on only
using __aarch64__.)

Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200
Signed-off-by: default avatarJulius Werner <jwerner@chromium.org>
      402b3cf8
  15. 05 Jun, 2019 1 commit
    • James kung's avatar
      Prevent pending G1S interrupt become G0 interrupt · acc29852
      James kung authored 
      

According to Arm GIC spec(IHI0069E, section 4.6.1),
when GICD_CTLR.DS == 0, Secure Group 1 interrupts
are treated as Group 0 by a CPU interface if:
- The PE does not implement EL3.
- ICC_SRE_EL1(S).SRE == 0

When a cpu enter suspend or deep idle, it might be
powered off. When the cpu resume, according to
the GIC spec(IHI0069E, section 9.2.15, 9.2.16 and
9.2.22) the ICC_SRE_EL1.SRE reset value is 0 (if
write is allowed) and G0/G1S/G1NS interrupt of the
GIC cpu interface are all disabled.

If a G1S SPI interrupt occurred and the target cpu
of the SPI is assigned to a specific cpu which is
in suspend and is powered off, when the cpu resume
and start to initial the GIC cpu interface, the
initial sequence might affect the interrupt group
type of the pending interrupt on the cpu interface.

Current initial sequence on the cpu interface is:
1. Enable G0 interrupt
2. Enable G1S interrupt
3. Enable ICC_SRE_EL1(S).SRE

It is possible to treat the pending G1S interrupt
as G0 interrupt on the cpu interface if the G1S
SPI interrupt occurred between step2 and step3.

To prevent the above situation happend, the initial
sequence should be changed as follows:
1. Enable ICC_SRE_EL1(S).SRE
2. Enable G0 interrupt
3. Enable G1S interrupt

Change-Id: Ie34f6e0b32eb9a1677ff72571fd4bfdb5cae25b0
Signed-off-by: default avatarJames Kung <kong1191@gmail.com>
      acc29852
  17. 04 Feb, 2019 1 commit
    • Soby Mathew's avatar
      GICv3: Allow probe for fewer GICR interfaces than exposed by the frame · 5dc2c3f9
      Soby Mathew authored 
      

Previously the GICv3 redistributor probe function
(gicv3_rdistif_base_addrs_probe()) asserted that the number of
per-CPU redistributor interfaces expected to be probed by the
platform is equal to the number exported by the redistributor
frame. This is a problem in case the number of CPUs in the
platform is less than the number of redistributor interfaces
in the frame. Hence this patch removes the assertion check
and allows probe for fewer redistributor interfaces as required
by the platform.

Change-Id: I3449763a3ad70817224442cbe184d001030c9874
Signed-off-by: default avatarSoby Mathew <soby.mathew@arm.com>
      5dc2c3f9
  19. 04 Jan, 2019 1 commit
    • Antonio Nino Diaz's avatar
      Sanitise includes across codebase · 09d40e0e
      Antonio Nino Diaz authored 
      Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca339

 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      09d40e0e
  21. 08 Nov, 2018 1 commit
    • Antonio Nino Diaz's avatar
      Standardise header guards across codebase · c3cf06f1
      Antonio Nino Diaz authored 
      

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.

The exceptions are files that are imported from other projects:

- CryptoCell driver
- dt-bindings folders
- zlib headers

Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      c3cf06f1
  23. 03 Oct, 2018 1 commit
  25. 28 Sep, 2018 1 commit
  27. 30 Aug, 2018 5 commits
  29. 26 Jul, 2018 1 commit
  31. 12 Jun, 2018 2 commits
    • Daniel Boulby's avatar
      Fix MISRA Rule 5.3 Part 2 · 896a5902
      Daniel Boulby authored 
      

Use a _ prefix for Macro arguments to prevent that argument from
hiding variables of the same name in the outer scope

Rule 5.3: An identifier declared in an inner scope shall not
          hide an identifier declared in an outer scope

Fixed For:
    make LOG_LEVEL=50 PLAT=fvp

Change-Id: I67b6b05cbad4aeca65ce52981b4679b340604708
Signed-off-by: default avatarDaniel Boulby <daniel.boulby@arm.com>
      896a5902
    • Daniel Boulby's avatar
      Fix MISRA Rule 5.1 · 87d3aacc
      Daniel Boulby authored 
      

Rule 5.1: External identifiers shall be distinct

Some of the identifier names in the GICv3 driver were so long that the
first 31 characters were identical. This patch shortens these names to
make sure they are different.

Fixed for:
    LOG_LEVEL=50 PLAT=fvp

Change-Id: Iecd551e3a015d144716b87b42c83dd3ab8c34d90
Signed-off-by: default avatarDaniel Boulby <daniel.boulby@arm.com>
      87d3aacc
  33. 03 Apr, 2018 1 commit
    • Andre Przywara's avatar
      gicv3: Fix support for systems without secure interrupts · 205cf6e7
      Andre Przywara authored 
      

Accessing the interrupt_props array only happens inside a loop over
interrupt_props_num, so the GICv3 driver can cope with no secure
interrupts. This allows us to relax the asserts that insists on
a non-NULL interrupt_props pointer and at least one secure interrupt.
This enables GICv3 platforms which have no need for a secure interrupt.

This only covers the non-deprecated code paths.

Change-Id: I49db291906512f56af065772f69acb281dfbdcfb
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      205cf6e7
  35. 26 Mar, 2018 2 commits
  37. 01 Mar, 2018 1 commit
    • Dan Handley's avatar
      Emit warnings when using deprecated GIC init · dcf01a0a
      Dan Handley authored 
      

Emit runtime warnings when intializing the GIC drivers using the
deprecated method of defining integer interrupt arrays in the GIC driver
data structures; interrupt_prop_t arrays should be used instead. This
helps platforms detect that they have migration work to do. Previously,
no warning was emitted in this case. This affects both the GICv2 and GICv3
drivers.

Also use the __deprecated attribute to emit a build time warning if these
deprecated fields are used. These warnings are suppressed in the GIC
driver compatibility functions but will be visible if platforms use them.

Change-Id: I6b6b8f6c3b4920c448b6dcb82fc18442cfdf6c7a
Signed-off-by: default avatarDan Handley <dan.handley@arm.com>
      dcf01a0a
  39. 28 Feb, 2018 1 commit
  41. 24 Jan, 2018 1 commit
  43. 13 Nov, 2017 1 commit
    • Jeenu Viswambharan's avatar
      GIC: Fix Group 0 enabling · 385f1dbb
      Jeenu Viswambharan authored 
      

At present, the GIC drivers enable Group 0 interrupts only if there are
Secure SPIs listed in the interrupt properties/list. This means that,
even if there are Group 0 SGIs/PPIs configured, the group remained
disabled in the absence of a Group 0 SPI.

Modify both GICv2 and GICv3 SGI/PPI configuration to enable Group 0 when
corresponding SGIs/PPIs are present.

Change-Id: Id123e8aaee0c22b476eebe3800340906d83bbc6d
Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      385f1dbb
  45. 16 Oct, 2017 11 commits
  47. 06 Oct, 2017 1 commit