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The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.

Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Running TF-A from non-standard location such as DRAM is useful for some
SRAM heavy use-cases. Allow the TF-A binary to be executed from an
arbitrary memory location.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Icd97926e4d97f37d7cde4a92758a52f57d569111

These errors are asynchronous and cannot be directly correlated with the
exact current running software, so handling them in the same EL is not
critical. Handling them in TF-A allows for more platform specific
decoding of the implementation defined exception registers
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Iee7a38c9fc9c698fa0ad42dafa598bcbed6a4fda

The new API becomes the default one.

Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

We previously left our caches on during power-down to prevent any
non-caching accesses to memory that is cached by other cores. Now with
the last accessed areas all being marked as non-cached by
USE_COHERENT_MEM we can rely on that to workaround our interconnect
issues. Remove the old workaround.

Change-Id: Idadb7696d1449499d1edff4f6f62ab3b99d1efb7
Signed-off-by: Andrew F. Davis <afd@ti.com>

HW_ASSISTED_COHERENCY implies something stronger than just hardware
coherent interconnect, specifically a DynamIQ capable ARM core.

For K3, lets use WARMBOOT_ENABLE_DCACHE_EARLY to enable caches early
and then let the caches get shut off on powerdown, to prevent data
corruption we also need to USE_COHERENT_MEM so that any accesses to
shared memory after this point is only to memory that is set as
non-cached for all cores.

Change-Id: Ib9337f012df0e0388237942607c501b6f3e2a949
Signed-off-by: Andrew F. Davis <afd@ti.com>

The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 access. Set the latency here for all A72 cores.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Id534316dec1c1f326908efbfd964f219cda7386a

Enable Cortex-A72 support for J721E.

Change-Id: I5bea5fb6ec45d1a9f8f2192d42da2cc03ae0f7ec
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

The MSMC port defines were added to help in the case when some ports
are not connected and have no cores attached. We can get the same
functionality by defined the number of cores on that port to zero.
This simplifies several code paths, do this here.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I3247fe37af7b86c3227e647b4f617fab70c8ee8a

These sections of code are only needed for the coherency workaround
used for AM65x, if this workaround is not needed then this code
is not either. Mark it off to keep it separated from the rest of
the PSCI implementation.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I113ca6a2a1f7881814ab0a64e5bac57139bc03ef

To make the USE_COHERENT_MEM option work we need to add an entry for the
area to our memory map table. Also fixup the alignment here.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I1c05477a97646ac73846a711bc38d3746628d847

The size of the RO data area was calculated by subtracting the area end
address from itself and not the base address due to a typo. Fix this
here.

Note, this was noticed at a glance thanks to the new aligned formating
of this table.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I994022ac9fc95dc5e37a420714da76081c61cce7

This macro was used when many of these functions were stubbed out,
the macro is not used anymore, remove it.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ida33f92fe3810a89e6e51faf6e93c1d2ada1a2ee

When we get a sequence ID that does not match what we expect then the we
are looking at is not the one we are expecting and so we error out. We
can also assume this message is a stale message left in the queue, in
this case we can read in the next message and check again for our
message. Switch to doing that here. We only retry a set number of times
so we don't lock the system if our message is actually lost and will
never show up.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I6c8186ccc45e646d3ba9d431f7d4c451dcd70c5c

The sequence ID can be set with a message to identify it when it is
responded to in the response queue. We assign each message a number and
check for this same number to detect response mismatches.

Start this at 0 and increase it by one for each message sent, even ones
that do not request or wait for a response as one may still be delivered
in some cases and we want to detect this.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I72b4d1ef98bf1c1409d9db9db074af8dfbcd83ea

The direction of a thread should be explicitly compared to avoid
confusion. Also fixup message wording based on this direction.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ia3cf9413cd23af476bb5d2e6d70bee15234cbd11

The ID of a thread is not used outside for printing it out when
something goes wrong. The specifier used is also not consistent.
Instead of storing the thread ID, store its name and print that.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Id137c2f8dfdd5c599e220193344ece903f80af7b

This is only a formatting change but makes it instantly clear how each
region is set. This is over 80 chars and the MT_RO are not strictly
needed but this section very important to get right so make readability
the priority here.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I2432deda05d4502b3478170296b5da43f26ad8e6

This should be more secure and looks a bit cleaner.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ie5eaf0234b211ba02631cf5eab5faa1402a34461

We don't use this for anything right now, remove it.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I11505d01834f7ff1fdba46fda0acbb3b56fc9b66

This makes definitions more consistent, plus helps alignment.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I38fcdd76207586613d9934c9dc83d7a347e9e0fc

ATF should be the only host needing to control a processor that it has
started. ATF will need this control to stop the core later. Do not
relinquish control of a core after starting the core.
Signed-off-by: Andrew F. Davis <afd@ti.com>

Now that we have non-blocking TI-SCI functions we can initiate the shutdown
sequence from the PSCI handler without needing the ti_sci_proc_shutdown
helper function, which is removed. This gives us the greater control and
flexibility that will be needed when cluster power down sequences are added.
Signed-off-by: Andrew F. Davis <afd@ti.com>

Most TI-SCI functions request an ACK and wait until it is received. For
some power sequence tasks we cannot wait but instead queue messages
asynchronously. Three messages have been identified that will need to
be used in this way. Add non-waiting versions of these functions.
Signed-off-by: Andrew F. Davis <afd@ti.com>

Currently almost all TI-SCI messages request and check for an ACK from
the system firmware. Move this into a common place to remove the same
from each function.
Signed-off-by: Andrew F. Davis <afd@ti.com>

When a device is requested with TI-SCI its control can be made exclusive
to the requesting host. This was currently the default but is not what
is needed most of the time. Add _exclusive versions of the request
functions and remove the exclusive flag from the default version.
Signed-off-by: Andrew F. Davis <afd@ti.com>

The raw get and set state functions for both devices and clocks
are only meant for use internal to the TI-SCI driver, the same
functionality is available from the other API that call into
these. Remove them from the external interface and make them
static scope to the driver.
Signed-off-by: Andrew F. Davis <afd@ti.com>

Valid addresses for GICR base are always a set calculable distance from
the GICD and is based on the number of cores a given instance of GICv3 IP
can support. The formula for the number of address bits is given by the
ARM GIC-500 TRM section 3.2 as 2^(18+log2(cores)) with the MSB set to
one for GICR instances. Holes in the GIC address space are also
guaranteed to safely return 0 on reads. This allows us to support runtime
detection of the GICR base address by starting from GIC base address plus
BIT(18) and walking until the GICR ID register (IIDR) is detected. We
stop searching after BIT(20) to prevent searching out into space if
something goes wrong. This can be extended out if we ever have a device
with 16 or more cores.
Signed-off-by: Andrew F. Davis <afd@ti.com>

To accommodate scenarios where we want to use a UART baud rate other than
the default 115,200 allow the associated compiler definition to be set
via the K3_USART_BAUD build option by updating the platform make file.

Since the platform make file now also contains the default value (still
115,200), go ahead and remove the redundant definition from the platform
header file.
Suggested-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>

Send and receive currently must be be serialized, any message already in
the receive queue when a new message is to be sent will cause a mismatch
with the expected response from this new message. Clear out all messages
from the response queue before sending a new request.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

It can be needed to discard all messages in a receive queue. This
can be used during some error recovery situations.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

To ensure WFI is reached before the PSC is trigger to power-down
a processor, the shutdonw API must be used.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

This is a pseudo-API command consisting of a wait processor status
command and a set device state command queued back-to-back without
waiting for the System Firmware to ACK either message.

This is needed as the K3 power down specification states the System
Firmware must wait for a processor to be in WFI/WFE before powering
it down. The current implementation of System Firmware does not provide
such a command. Also given that with PSCI the core to be shutdown is the
core that is processing the shutdown request, the core cannot itself wait
for its own WFI/WFE status. To workaround this limitation, we submit
a wait processor status command followed by the actual shutdown command.
The shutdown command will not be processed until the wait command has
finished. In this way we can continue to WFI before the wait command
status has been met or timed-out and the shutdown command is processed.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

This TI-SCI API can be used wait for a set of processor status flags to
be set or cleared. The flags are processor type specific. This command
will not return ACK until the specified status is met. NACK will be
returned after the timeout elapses or on error.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

The logic is correct here, but the error messages are
reversed, switch them.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca339

 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

This patch makes the build system link the console framework code by
default, like it already does with other common libraries (e.g. cache
helpers). This should not make a difference in practice since TF is
linked with --gc-sections, so the linker will garbage collect all
functions and data that are not referenced by any other code. Thus, if a
platform doesn't want to include console code for size reasons and
doesn't make any references to console functions, the code will not be
included in the final binary.

To avoid compatibility issues with older platform ports, only make this
change for the MULTI_CONSOLE_API.

Change-Id: I153a9dbe680d57aadb860d1c829759ba701130d3
Signed-off-by: Julius Werner <jwerner@chromium.org>

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.

The exceptions are files that are imported from other projects:

- CryptoCell driver
- dt-bindings folders
- zlib headers

Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

A recent patch[0] has made setting up page tables into generic
code, complete the conversion for TI platforms by removing the
use of plat_arm_get_mmap() and using the mmap table directly.

[0] 0916c38d

 ("Convert arm_setup_page_tables into a generic helper")
Signed-off-by: Andrew F. Davis <afd@ti.com>

This function is not related to Arm platforms and can be reused by other
platforms if needed.

Change-Id: Ia9c328ce57ce7e917b825a9e09a42b0abb1a53e8
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>