- 20 Jul, 2018 1 commit
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Antonio Nino Diaz authored
Also change header guards to fix defects of MISRA C-2012 Rule 21.1. Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 21 Jun, 2018 1 commit
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Siva Durga Prasad Paladugu authored
This patch builds ATF to DDR if SPD is enabled as it cant fit in On chip memory(OCM) with SPD enabled. This solves the issue of build failure with SPD enabled for ZynqMP platform. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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- 17 May, 2018 1 commit
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Siva Durga Prasad Paladugu authored
This patch adds support to restart system incase of wdt timeout. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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- 15 Mar, 2018 1 commit
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Jolly Shah authored
Define default DDR location to which ATF has to compiled if DEBUG option is enabled. This is required now, as the ATF cant fit in OCM with DEBUG option enabled. The default value is 0x1000 and can be used till 0x7ffff. User can still override as per wish/requirement using current commandline options. Signed-off-by: Jolly Shah <jollys@xilinx.com>
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- 27 Feb, 2018 1 commit
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David Cunado authored
MISRA C-2012 Rule 7.3 violation: lowercase l shall not be used as literal suffixes. This patch resolves this for the ULL() macro by using ULL suffix instead of the ull suffix. Change-Id: Ia8183c399e74677e676956e8653e82375d0e0a01 Signed-off-by: David Cunado <david.cunado@arm.com>
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- 17 Oct, 2017 1 commit
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Jeenu Viswambharan authored
Change-Id: Ia8503d446cc8b4246013046f6294fea364c9c882 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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- 03 May, 2017 1 commit
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dp-arm authored
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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- 06 Jan, 2017 1 commit
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Soren Brinkmann authored
Commit 0029624f ("Add PLAT_xxx_ADDR_SPACE_SIZE definition") deprecates 'ADDR_SPACE_SIZE' in favor of PLAT_(PHY|VIRT)_ADDRESS_SPACE_SIZE. Migrate the zynqmp platform to use the new interface. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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- 16 Nov, 2016 1 commit
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Soren Brinkmann authored
Remove dead code pieces and stale comments. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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- 13 Sep, 2016 2 commits
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Soren Brinkmann authored
When moving the ATF into the DRAM address space an additional translation table is required. Reported-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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Soren Brinkmann authored
The OCM space was reorganized to use the space more efficiently. Adjust the default ATF location to be aligned with other ZynqMP software components. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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- 11 Jul, 2016 1 commit
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Soren Brinkmann authored
Set the SEPARATE_CODE_AND_RODATA build flag to map read-only data as execute never. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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- 24 May, 2016 1 commit
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Soren Brinkmann authored
The GIC area is specified larger than it needs to be and can be reduced. Which allows reducing the structures required for the translation tables as well. This results in a reduction of memory footprint of ca. 4k. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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- 25 Apr, 2016 1 commit
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Soren Brinkmann authored
Drop the current configuration options for selecting the location of the ATF and TSP (ZYNQMP_ATF_LOCATION, ZYNQMP_TSP_RAM_LOCATION). The new configuration provides one default setup (ATF in OCM, BL32 in DRAM). Additionally, the new configuration options - ZYNQMP_ATF_MEM_BASE - ZYNQMP_ATF_MEM_SIZE - ZYNQMP_BL32_MEM_BASE - ZYNQMP_BL32_MEM_SIZE can be used to freely configure the memory locations used for ATF and secure payload. Also, allow setting the BL33 entry point via PRELOADED_BL33_BASE. Cc: petalinux-dev@xilinx.com Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Alistair Francis <alistair.francis@xilinx.com>
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- 14 Apr, 2016 1 commit
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Gerald Lejeune authored
It is up to the platform to implement the new plat_crash_print_regs macro to report all relevant platform registers helpful for troubleshooting. plat_crash_print_regs merges or calls previously defined plat_print_gic_regs and plat_print_interconnect_regs macros for each existing platforms. NOTE: THIS COMMIT REQUIRES ALL PLATFORMS THAT ENABLE THE `CRASH_REPORTING` BUILD FLAG TO MIGRATE TO USE THE NEW `plat_crash_print_regs()` MACRO. BY DEFAULT, `CRASH_REPORTING` IS ENABLED IN DEBUG BUILDS FOR ALL PLATFORMS. Fixes: arm-software/tf-issues#373 Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
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- 06 Apr, 2016 1 commit
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Soren Brinkmann authored
The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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