1. 28 Jun, 2019 1 commit
  2. 26 Jun, 2019 1 commit
  3. 24 May, 2019 1 commit
    • Alexei Fedorov's avatar
      Add support for Branch Target Identification · 9fc59639
      Alexei Fedorov authored
      
      
      This patch adds the functionality needed for platforms to provide
      Branch Target Identification (BTI) extension, introduced to AArch64
      in Armv8.5-A by adding BTI instruction used to mark valid targets
      for indirect branches. The patch sets new GP bit [50] to the stage 1
      Translation Table Block and Page entries to denote guarded EL3 code
      pages which will cause processor to trap instructions in protected
      pages trying to perform an indirect branch to any instruction other
      than BTI.
      BTI feature is selected by BRANCH_PROTECTION option which supersedes
      the previous ENABLE_PAUTH used for Armv8.3-A Pointer Authentication
      and is disabled by default. Enabling BTI requires compiler support
      and was tested with GCC versions 9.0.0, 9.0.1 and 10.0.0.
      The assembly macros and helpers are modified to accommodate the BTI
      instruction.
      This is an experimental feature.
      Note. The previous ENABLE_PAUTH build option to enable PAuth in EL3
      is now made as an internal flag and BRANCH_PROTECTION flag should be
      used instead to enable Pointer Authentication.
      Note. USE_LIBROM=1 option is currently not supported.
      
      Change-Id: Ifaf4438609b16647dc79468b70cd1f47a623362e
      Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      9fc59639
  4. 02 May, 2019 1 commit
    • Christoph Müllner's avatar
      build_macros: Add mechanism to prevent bin generation. · 9e4609f1
      Christoph Müllner authored
      
      
      On certain platforms it does not make sense to generate
      TF-A binary images. For example a platform could make use of serveral
      memory areas, which are non-continuous and the resulting binary
      therefore would suffer from the padding-bytes.
      Typically these platforms use the ELF image.
      
      This patch introduces a variable DISABLE_BIN_GENERATION, which
      can be set to '1' in the platform makefile to prevent the binary
      generation.
      Signed-off-by: default avatarChristoph Müllner <christophm30@gmail.com>
      Change-Id: I62948e88bab685bb055fe6167d9660d14e604462
      9e4609f1
  5. 28 Feb, 2019 1 commit
  6. 27 Feb, 2019 3 commits
    • Varun Wadekar's avatar
      Tegra: Support for scatterfile for the BL31 image · c2ad38ce
      Varun Wadekar authored
      
      
      This patch provides support for using the scatterfile format as
      the linker script with the 'armlink' linker for Tegra platforms.
      
      In order to enable the scatterfile usage the following changes
      have been made:
      
      * provide mapping for ld.S symbols in bl_common.h
      * include bl_common.h from all the affected files
      * update the makefile rules to use the scatterfile and armlink
        to compile BL31
      * update pubsub.h to add sections to the scatterfile
      
      NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY.
      
      Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      c2ad38ce
    • Antonio Nino Diaz's avatar
      Add support for pointer authentication · b86048c4
      Antonio Nino Diaz authored
      
      
      The previous commit added the infrastructure to load and save
      ARMv8.3-PAuth registers during Non-secure <-> Secure world switches, but
      didn't actually enable pointer authentication in the firmware.
      
      This patch adds the functionality needed for platforms to provide
      authentication keys for the firmware, and a new option (ENABLE_PAUTH) to
      enable pointer authentication in the firmware itself. This option is
      disabled by default, and it requires CTX_INCLUDE_PAUTH_REGS to be
      enabled.
      
      Change-Id: I35127ec271e1198d43209044de39fa712ef202a5
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      b86048c4
    • Antonio Nino Diaz's avatar
      Add ARMv8.3-PAuth registers to CPU context · 5283962e
      Antonio Nino Diaz authored
      
      
      ARMv8.3-PAuth adds functionality that supports address authentication of
      the contents of a register before that register is used as the target of
      an indirect branch, or as a load.
      
      This feature is supported only in AArch64 state.
      
      This feature is mandatory in ARMv8.3 implementations.
      
      This feature adds several registers to EL1. A new option called
      CTX_INCLUDE_PAUTH_REGS has been added to select if the TF needs to save
      them during Non-secure <-> Secure world switches. This option must be
      enabled if the hardware has the registers or the values will be leaked
      during world switches.
      
      To prevent leaks, this patch also disables pointer authentication in the
      Secure world if CTX_INCLUDE_PAUTH_REGS is 0. Any attempt to use it will
      be trapped in EL3.
      
      Change-Id: I27beba9907b9a86c6df1d0c5bf6180c972830855
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      5283962e
  7. 19 Feb, 2019 1 commit
  8. 08 Feb, 2019 1 commit
  9. 05 Feb, 2019 1 commit
  10. 30 Jan, 2019 1 commit
  11. 24 Jan, 2019 1 commit
    • Manish Pandey's avatar
      Make device tree pre-processing similar to U-boot/Linux · 7e94a699
      Manish Pandey authored
      
      
      Following changes are done to make DT pre-processing similar to that of
      U-boot/Linux kernel.
      
      1. Creating seperate CPPFLAGS for DT preprocessing so that compiler
      options specific to it can be accommodated.
      e.g: "-undef" compiler option avoids replacing "linux" string(used in
      device trees) with "1" as "linux" is a pre-defined macro in gnu99
      standard.
      
      2. Replace CPP with PP for DT pre-processing, as CPP in U-boot/Linux is
      exported as "${CROSS_COMPILE}gcc -E" while in TF-A it is exported as
      "${CROSS_COMPILE}cpp".
      
      Change-Id: If4c61a249d51614d9f53ae30b602036d50c02349
      Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
      7e94a699
  12. 22 Jan, 2019 1 commit
  13. 10 Jan, 2019 1 commit
  14. 10 Dec, 2018 1 commit
    • Antonio Nino Diaz's avatar
      SPM: Deprecate the current implementation · 2d7b9e5e
      Antonio Nino Diaz authored
      
      
      The current SPM is a prototype that only supports one secure partition
      in EL0. The objective of SPM is to have multiple partitions. The current
      MM interface isn't adequate for this, so it is needed to modify heavily
      the code to add proper support for it.
      
      However, there are platforms which are already using this (like SGI) and
      removing the code would break it.  For this reason, the current SPM code
      has been duplicated in order to temporarily preserve compatibility. All
      new improvements/changes to SPM will be done in the non-deprecated copy,
      that may change without notice.
      
      The new build option SPM_DEPRECATED has been introduced to select the SPM
      implementation. It defaults to 1, that selects the deprecated SPM.
      
      Change-Id: Ic9f80b53b450e97b4d3f47e4ef4a138ee8d87443
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      2d7b9e5e
  15. 22 Nov, 2018 1 commit
    • Sathees Balya's avatar
      romlib: Allow patching of romlib functions · 6baf85b3
      Sathees Balya authored
      
      
      This change allows patching of functions in the
      romlib. This can be done by adding "patch" at the
      end of the jump table entry for the function that
      needs to be patched in the file jmptbl.i.
      Functions patched in the jump table list will be
      built as part of the BL image and the romlib
      version will not be used
      
      Change-Id: Iefb200cb86e2a4b61ad3ee6180d3ecc39bad537f
      Signed-off-by: default avatarSathees Balya <sathees.balya@arm.com>
      6baf85b3
  16. 29 Oct, 2018 1 commit
  17. 19 Oct, 2018 1 commit
  18. 08 Oct, 2018 1 commit
    • Andre Przywara's avatar
      Makefile: Support totally quiet output with -s · ee1ba6d4
      Andre Przywara authored
      
      
      "-s" is a command line option to the make tool, to suppress normal output,
      something to the effect of prepending every line with '@' in the Makefile.
      However with our V={0|1} support, we now print the shortened command line
      output in any case (even with V=1, in addition to the long line!).
      Normally -s helps to not miss non-fatal warnings, which tend to scroll out
      of the window easily.
      
      Introduce a new Makefile variable ECHO, to control the shortened output.
      We only set it in the (current default) V=0 case, and replace every
      occurence of "@echo" with that variable.
      When the user specifies "-s", we set ECHO to some magic string which
      changes the output line into a comment, so the output is suppressed.
      
      Beside suppressing every output for "-s", we also avoid the redundant
      short output when compiling with V=1.
      
      This changes the output to:
      ==========
      $ make -s PLAT=.... bl31
      
      Built build/.../release/bl31.bin
      
      ==========
      $ make PLAT=.... bl31
      ...
        CC      lib/libc/strncmp.c
        CC      lib/libc/strnlen.c
      ...
      ==========
      $ make V=1 PLAT=.... bl31
      ...
      gcc -DDEBUG=0 .... -o build/.../release/libc/strncmp.o
      gcc -DDEBUG=0 .... -o build/.../release/libc/strnlen.o
      ...
      ==========
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      ee1ba6d4
  19. 03 Oct, 2018 2 commits
  20. 28 Sep, 2018 4 commits
  21. 30 Aug, 2018 1 commit
    • Antonio Nino Diaz's avatar
      Allow manually setting the AArch32 instruction set · 8fd9d4d5
      Antonio Nino Diaz authored
      
      
      At the moment the AArch32 instruction set isn't specified in the command
      line, which means that the compiler is free to choose the one it sees
      fit. This decision may change between compiler versions, so it is better
      to specify it manually.
      
      The build option AARCH32_INSTRUCTION_SET has been introduced for this
      reason. This option can be set to T32 or A32 to pass the correct flags
      to the compiler.
      
      The current behaviour is to default to T32 due to it's smaller size.
      
      Change-Id: I02297eb1d9404b5868ff7c054fbff9b3cda7fdb6
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      8fd9d4d5
  22. 20 Aug, 2018 1 commit
    • Jeenu Viswambharan's avatar
      AArch64: Enable MPAM for lower ELs · 5f835918
      Jeenu Viswambharan authored
      
      
      Memory Partitioning And Monitoring is an Armv8.4 feature that enables
      various memory system components and resources to define partitions.
      Software running at various ELs can then assign themselves to the
      desired partition to control their performance aspects.
      
      With this patch, when ENABLE_MPAM_FOR_LOWER_ELS is set to 1, EL3 allows
      lower ELs to access their own MPAM registers without trapping to EL3.
      This patch however doesn't make use of partitioning in EL3; platform
      initialisation code should configure and use partitions in EL3 if
      required.
      
      Change-Id: I5a55b6771ccaa0c1cffc05543d2116b60cbbcdcd
      Co-authored-by: default avatarJames Morse <james.morse@arm.com>
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      5f835918
  23. 03 Aug, 2018 2 commits
    • Roberto Vargas's avatar
      Add support for romlib in the build system · 5accce5b
      Roberto Vargas authored
      
      
      Romlib is a new image that is stored in ROM and contains the code of
      several libraries that can be shared between different images. All
      the functions within in the library are accessed using a jump table
      which allows to update the romlib image whithout changing the binary
      compatibility. This jump table can be also stored in RAM and it can
      allow to patch a romlib with potential bugs fixes..
      
      Change-Id: If980ccdaca24b7aaca900e32acc68baf6f94ab35
      Signed-off-by: default avatarRoberto Vargas <roberto.vargas@arm.com>
      5accce5b
    • Roberto Vargas's avatar
      Add make macros to build library archives · 5fee0287
      Roberto Vargas authored
      
      
      This patch adds all the make macros needed to create a library archive
      and to use it in the link stage.
      
      Change-Id: I26597bfd6543649d0b68a9b1e06aec1ba353e6de
      Signed-off-by: default avatarRoberto Vargas <roberto.vargas@arm.com>
      5fee0287
  24. 18 Jul, 2018 1 commit
    • Konstantin Porotchkin's avatar
      make: support libraries in MAKE_BL macro · 23e0fe52
      Konstantin Porotchkin authored
      
      
      Add support for BLx stages to use libraries in MAKE_BL macro.
      This change does not affect BL stages that do not have
      BL_LIBS variable defined in their makefiles.
      However in case that BL wants to use external library
      (for instance vendor-specific DDR initialization code supplied
      as a library), this patch will allow to build BL image linked
      with such library.
      
      Change-Id: Ife29069a72dc4aff833db6ef8b828736d6689b78
      Signed-off-by: default avatarKonstantin Porotchkin <kostap@marvell.com>
      23e0fe52
  25. 18 Jun, 2018 1 commit
    • Yann Gautier's avatar
      Build: add cpp build processing for dtb · 01d237cb
      Yann Gautier authored
      
      
      This is an add-on feature that allows processing
      device tree with external includes.
      
      "-Iinclude" is also added to INCLUDES.
      It allows inclusion of dt-bindings files either in dts files or drivers,
      as those files will be in include/dt-bindings/.
      
      "-i fdts" is added to the DTC command line.
      As the pre-processed files are in build directory, the DT source directory
      has to be explicitely included, to manages /include/ directives.
      
      fixes arm-software/tf-issues#595
      Signed-off-by: default avatarLionel Debieve <lionel.debieve@st.com>
      Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      01d237cb
  26. 18 May, 2018 1 commit
  27. 04 May, 2018 3 commits
    • Jeenu Viswambharan's avatar
      RAS: Add fault injection support · 1a7c1cfe
      Jeenu Viswambharan authored
      
      
      The ARMv8.4 RAS extensions introduce architectural support for software
      to inject faults into the system in order to test fault-handling
      software. This patch introduces the build option FAULT_HANDLING_SUPPORT
      to allow for lower ELs to use registers in the Standard Error Record to
      inject fault. The build option RAS_EXTENSIONS must also be enabled along
      with fault injection.
      
      This feature is intended for testing purposes only, and is advisable to
      keep disabled for production images.
      
      Change-Id: I6f7a4454b15aec098f9505a10eb188c2f928f7ea
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      1a7c1cfe
    • Jeenu Viswambharan's avatar
      AArch64: Introduce RAS handling · 14c6016a
      Jeenu Viswambharan authored
      
      
      RAS extensions are mandatory for ARMv8.2 CPUs, but are also optional
      extensions to base ARMv8.0 architecture.
      
      This patch adds build system support to enable RAS features in ARM
      Trusted Firmware. A boolean build option RAS_EXTENSION is introduced for
      this.
      
      With RAS_EXTENSION, an Exception Synchronization Barrier (ESB) is
      inserted at all EL3 vector entry and exit. ESBs will synchronize pending
      external aborts before entering EL3, and therefore will contain and
      attribute errors to lower EL execution. Any errors thus synchronized are
      detected via. DISR_EL1 register.
      
      When RAS_EXTENSION is set to 1, HANDLE_EL3_EA_FIRST must also be set to 1.
      
      Change-Id: I38a19d84014d4d8af688bd81d61ba582c039383a
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      14c6016a
    • Jeenu Viswambharan's avatar
      AArch64: Introduce External Abort handling · 76454abf
      Jeenu Viswambharan authored
      
      
      At present, any External Abort routed to EL3 is reported as an unhandled
      exception and cause a panic. This patch enables ARM Trusted Firmware to
      handle External Aborts routed to EL3.
      
      With this patch, when an External Abort is received at EL3, its handling
      is delegated to plat_ea_handler() function. Platforms can provide their
      own implementation of this function. This patch adds a weak definition
      of the said function that prints out a message and just panics.
      
      In order to support handling External Aborts at EL3, the build option
      HANDLE_EA_EL3_FIRST must be set to 1.
      
      Before this patch, HANDLE_EA_EL3_FIRST wasn't passed down to
      compilation; this patch fixes that too.
      
      Change-Id: I4d07b7e65eb191ff72d63b909ae9512478cd01a1
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      76454abf
  28. 23 Apr, 2018 1 commit
    • Antonio Nino Diaz's avatar
      Add support for the SMC Calling Convention 2.0 · 2f370465
      Antonio Nino Diaz authored
      
      
      Due to differences in the bitfields of the SMC IDs, it is not possible
      to support SMCCC 1.X and 2.0 at the same time.
      
      The behaviour of `SMCCC_MAJOR_VERSION` has changed. Now, it is a build
      option that specifies the major version of the SMCCC that the Trusted
      Firmware supports. The only two allowed values are 1 and 2, and it
      defaults to 1. The value of `SMCCC_MINOR_VERSION` is derived from it.
      
      Note: Support for SMCCC v2.0 is an experimental feature to enable
      prototyping of secure partition specifications. Support for this
      convention is disabled by default and could be removed without notice.
      
      Change-Id: I88abf9ccf08e9c66a13ce55c890edea54d9f16a7
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      2f370465
  29. 07 Apr, 2018 1 commit
    • Jiafei Pan's avatar
      Add support for BL2 in XIP memory · 7d173fc5
      Jiafei Pan authored
      
      
      In some use-cases BL2 will be stored in eXecute In Place (XIP) memory,
      like BL1. In these use-cases, it is necessary to initialize the RW sections
      in RAM, while leaving the RO sections in place. This patch enable this
      use-case with a new build option, BL2_IN_XIP_MEM. For now, this option
      is only supported when BL2_AT_EL3 is 1.
      Signed-off-by: default avatarJiafei Pan <Jiafei.Pan@nxp.com>
      7d173fc5
  30. 05 Mar, 2018 1 commit
  31. 01 Mar, 2018 1 commit