1. 20 Mar, 2018 1 commit
    • Michalis Pappas's avatar
      qemu: Add support for stack canary protection · f68d22e8
      Michalis Pappas authored
      
      
      Allow qemu users to enable stack protection. Since the virt platform
      does not provide an RNG, use a basic, timer-based, canary generation,
      similarly to FVP.
      
      Increase SRAM size and BL2 size to fit images when stack protection is
      enabled.
      
      Notice that stack protection is not enabled by default in qemu.
      
      Fixes ARM-software/tf-issues#568
      Signed-off-by: default avatarMichalis Pappas <mpappas@fastmail.fm>
      f68d22e8
  2. 04 Mar, 2018 1 commit
  3. 28 Feb, 2018 1 commit
    • Michalis Pappas's avatar
      qemu: Support SEPARATE_CODE_AND_RODATA · 27e0ccab
      Michalis Pappas authored
      
      
      Update qemu_configure_mmu_##_el to add an additional region for code,
      marked as MT_CODE | MT_SECURE. Update ro region attributes to NON_EXEC.
      
      Update calls to QEMU_CONFIGURE_BLx_MMU() to pass an additional region for
      code. Update calls to pass regions defined in common_def.h.
      
      Increase MAX_MMAP_REGIONS to 10.
      
      Enable SEPARATE_CODE_AND_RODATA by default on QEMU builds.
      
      Fixes ARM-software/tf-issues#558
      Signed-off-by: default avatarMichalis Pappas <mpappas@fastmail.fm>
      27e0ccab
  4. 27 Feb, 2018 1 commit
  5. 05 Feb, 2018 1 commit
    • Etienne Carriere's avatar
      qemu: support ARMv7/Cortex-A15 · 765ed9fc
      Etienne Carriere authored
      
      
      Define Qemu AArch32 implementation for some platform functions
      (core position, secondary boot cores, crash console). These are
      derived from the AArch64 implementation.
      
      BL31 on Qemu is needed only for ARMv8 and later. On ARMv7, BL32 is
      the first executable image after BL2.
      
      Support SP_MIN and OP-TEE as BL32: create a sp_min make script target
      in Qemu, define mapping for IMAGE_BL32
      
      Minor fix Qemu return value type for plat_get_ns_image_entrypoint().
      
      Qemu model for the Cortex-A15 does not support the virtualization
      extension although the core expects it. To overcome the issue, Qemu
      ARMv7 configuration set ARCH_SUPPORTS_VIRTUALIZATION to 0.
      
      Add missing AArch32 assembly macro arm_print_gic_regs from ARM platform
      used by the Qemu platform.
      
      Qemu Cortex-A15 model integrates a single cluster with up to 4 cores.
      
      Change-Id: I65b44399071d6f5aa40d5183be11422b9ee9ca15
      Signed-off-by: default avatarEtienne Carriere <etienne.carriere@linaro.org>
      765ed9fc
  6. 26 Oct, 2017 1 commit
  7. 24 Oct, 2017 1 commit
    • Etienne Carriere's avatar
      qemu: fix holding pen mailbox sequence · 33dd33f8
      Etienne Carriere authored
      
      
      Before this change, plat_secondary_cold_boot_setup reads wake up mailbox
      as a byte array but through 64bit accesses on unaligned 64bit addresses.
      In the other hand qemu_pwr_domain_on wakes secondary cores by writing
      into a 64bit array.
      
      This change forces the 64bit mailbox format as PLAT_QEMU_HOLD_ENTRY_SIZE
      explicitly specifies it.
      Signed-off-by: default avatarEtienne Carriere <etienne.carriere@linaro.org>
      33dd33f8
  8. 24 Aug, 2017 2 commits
  9. 03 May, 2017 1 commit
  10. 18 Jan, 2017 1 commit
  11. 09 Jun, 2016 1 commit