- 12 Feb, 2020 11 commits
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Masahiro Yamada authored
The on-chip SRAM region will be changed in the next SoC. Make it configurable. Also, split the mmap code into a new helper function so that it can be re-used for another boot mode. Change-Id: I89f40432bf852a58ebc9be5d9dec4136b8dc010b Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
The I/O register region will be changed in the next SoC. Make it configurable. Change-Id: Iec0cbd1ef2d0703ebc7c3d3082edd73791bbfec9 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
The next SoC will have: - No boot swap - SD boot - No USB boot Add new fields to handle this. Change-Id: I772395f2c5dfc612e575b0cbd0657a5fa9611c25 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
The register base address will be changed in the next SoC. Make it configurable. Change-Id: Ibe07bd9db128b0f7e629916cb6ae21ba7984eca9 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
The flag, uniphier_emmc_block_addressing, is boolean logic, so "bool' is more suitable. uniphier_emmc_is_over_2gb() is not boolean - it returns 1 / 0 depending on the card density, or a negative value on failure. Rename it to make it less confusing. Change-Id: Ia646b1929147b644e0df07c46b54ab80548bc3bd Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
The register base will be changed in the next SoC. Make it configurable. Change-Id: I4a7cf85fe50e4d71db58a3372a71774e43193bd3 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
This is boolean logic, so "bool" is more suitable. Change-Id: I439c5099770600a65b8f58390a4c621c2ee487a5 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
The next SoC supports the same UART, but the register base will be changed. Make it configurable. Change-Id: Ida5c9151b2f3554afd15555b22838437eef443f7 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
The register base will be changed in the next SoC. Make it configurable. Change-Id: I9fbb6bdd1cf06207618742d4ad7970d911c9bc26 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
The next SoC does not support the NAND controller, but make the base address configurable for consistency and future proof. Change-Id: I776e43ff2b0408577919b0b72849c3e1e5ce0758 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
The next SoC supports the same eMMC controller, but the register base will be changed. Make it configurable. Change-Id: I00cb5531bc3d8d49357ad5e922cdd3d785355edf Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 24 Jan, 2020 7 commits
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Masahiro Yamada authored
This platform supports multiple SoCs. The next SoC will still keep quite similar architecture, but the memory base will be changed. The ENABLE_PIE improves the maintainability and usability. You can reuse a single set of BL images for other SoC/board without re-compiling TF-A at all. This will also keep the code cleaner because it avoids #ifdef around various base addresses. By defining ENABLE_PIE, BL2_AT_EL3, BL31, and BL32 (TSP) are really position-independent now. You can load them anywhere irrespective of their link address. Change-Id: I8d5e3124ee30012f5b3bfa278b0baff8efd2fff7 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
BL2_BASE, BL31_BASE, and BL32_BASE are defined in platform_def.h, that is, determined at link-time. On the other hand, BL2_END, BL31_END, and BL32_END are derived from the symbols produced by the linker scripts. So, they are fixed-up at run-time if ENABLE_PIE is enabled. To make it work in a position-indepenent manner, use BL_CODE_BASE and BL_END, both of which are relocatable. Change-Id: Ic179a7c60eb64c5f3024b178690b3ac7cbd7521b Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Currently, UNIPHIER_SCP_BASE is hard-coded in uniphier_scp_start(), which is not handy for PIE. Towards the goal of making this really position-independent, pass in image_info->image_base. Change-Id: I88e020a1919c607b1d5ce70b116201d95773bb63 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Currently, the .buffer field in io_block_dev_spec is statically set, which is not handy for PIE. Towards the goal of making this really position-independent, set the buffer length and length in the uniphier_io_block_setup() function. Change-Id: I22b20d7b58d6ffd38f64f967a2820fca4bd7dade Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Currently, uniphier_bl2_mmap hard-codes the memory region needed for loading other images. Towards the goal of making this really position-independent, call mmap_add_dynamic_region() before that region gets accessed. Change-Id: Ieb505b91ccf2483e5f1a280accda564b33f19f11 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Now that various issues in the PIE support have been fixed, this platform can enable ENABLE_PIE. I tested BL2_AT_EL3, BL31, TSP, and all of them worked. Change-Id: Ibc499c6bad30b7f81a42bfa7e435ce25f820bd9c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Deepika Bhavnani authored
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Iad91e99e9d13254de23eb10e5f655253f253cf0d
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- 26 Dec, 2019 1 commit
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Masahiro Yamada authored
All the SoCs in 64-bit UniPhier SoC family support EL2. Just hard-code MODE_EL2 instead of using el_implemented() helper. Change-Id: I7ab48002c5205bc8c013e1b46313b57d6c431db0 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 25 Dec, 2019 1 commit
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Masahiro Yamada authored
uniphier_scp_is_running() reads the UNIPHIER_STMBE2COM register, but it does not exist on all SoCs. Do not call this function if the on-chip SCP is not supported. Change-Id: I7c71ca0735e3a8e095c3f22ba6165f82a2986362 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 03 Sep, 2019 1 commit
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Masahiro Yamada authored
This console driver sends '\r' before 'n', not after. It works, but the convention is "\r\n" (i.e. CRLF) Instead of fixing it in the driver, set CONSOLE_FLAG_TRANSLATE_CRLF to leave it to the framework. Change-Id: I2154e29313739a40dff70cfb5c0f8989136d4ad2 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 31 Jul, 2019 2 commits
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Masahiro Yamada authored
Fix the typo "warn" -> "warm". Also fix the following checkpatch.pl warnings: CHECK: Prefer using the BIT macro CHECK: No space is necessary after a cast CHECK: Alignment should match open parenthesis CHECK: Unnecessary parentheses around uniphier_io_policies[image_id].dev_handle Change-Id: Ic11eea2668c4bf2d1e8f089e6338ba7b7156d80b Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Use the helper in utils_def.h instead of the own macro. Change-Id: I527f9e75914d60f66354e365006b960ba5e8cbae Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 05 Jul, 2019 1 commit
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Masahiro Yamada authored
The legacy console is gone. Re-add the console support based on the multi-console framework. I am still keeping the putc, getc, and flush callbacks in uniphier_console.S to use plat/common/aarch64/crash_console_helpers.S The console registration code already relies on that C environment has been set up. So, I just filled the struct console fields with the callback pointers, then called console_register() directly. I also re-implemented the init function in C to improve the readability. Removing the custom crash console implementation has one disadvantage; we cannot use the crash console on very early crashes because crash_console_helpers.S works only after the console is registered. I can live with this limitation. Tested on my boards, and confirmed this worked like before. Change-Id: Ieab9c849853ff6c525c15ea894a85944f257db59 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 12 Apr, 2019 1 commit
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Ambroise Vincent authored
The implementation of the heap function plat_get_mbedtls_heap() becomes mandatory for platforms supporting TRUSTED_BOARD_BOOT. The shared Mbed TLS heap default weak function implementation is converted to a helper function get_mbedtls_heap_helper() which can be used by the platforms for their own function implementation. Change-Id: Ic8f2994e25e3d9fcd371a21ac459fdcafe07433e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 01 Feb, 2019 2 commits
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Antonio Nino Diaz authored
Also, update platform_def.h guidelines about includes in the porting guide. Change-Id: I1ae338c9dd3242b309f6d53687ba2cb755d488c3 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
Many parts of the code were duplicating symbols that are defined in include/common/bl_common.h. It is better to only use the definitions in this header. As all the symbols refer to virtual addresses, they have to be uintptr_t, not unsigned long. This has also been fixed in bl_common.h. Change-Id: I204081af78326ced03fb05f69846f229d324c711 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 04 Jan, 2019 1 commit
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Antonio Nino Diaz authored
Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca339 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 10 Dec, 2018 1 commit
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Yann Gautier authored
This is used as a table index, and already compared with an unsigned int: block_dev_count. Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 08 Nov, 2018 1 commit
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Antonio Nino Diaz authored
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 30 Oct, 2018 2 commits
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Dai Okamura authored
When the SoC issues a command IRQ to SCP, SCP sets STMTOBEIRQ as ACK. The SoC must wait for it before issuing the next command. This commit makes sure to meet the requirement. Signed-off-by: Dai Okamura <okamura.dai@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Skipping SCP_BL2 image is just a temporary workaround. If on-chip SCP needs to work, BL2 should load the SCP_BL2 image. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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- 28 Sep, 2018 1 commit
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Antonio Nino Diaz authored
- Remove references to removed build options. - Migrate to bl31_early_platform_setup2(). Change-Id: I9242c4d02a36e385bf0bf8ee56287106030153d1 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 30 Aug, 2018 1 commit
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Antonio Nino Diaz authored
Change-Id: I5993b425445ee794e6d2a792c244c0af53640655 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 22 Aug, 2018 1 commit
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Antonio Nino Diaz authored
The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers. Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 20 Jul, 2018 1 commit
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Antonio Nino Diaz authored
Also change header guards to fix defects of MISRA C-2012 Rule 21.1. Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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- 12 Jun, 2018 1 commit
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Satoshi Ikawa authored
The slave ports of LD20 CCI-500 are connected as follows: S0: CA53 S1: CA72 Be careful because the slave interface is not arranged in the cluster number order (CA72: cluster 0, CA53: cluster 1). Root-caused-by: Tetsuya Yoshizaki <yoshizaki.tetsuya@socionext.com> Signed-off-by: Satoshi Ikawa <ikawa.satoshi@socionext.com>
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- 26 Mar, 2018 1 commit
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Jonathan Wright authored
Ensure (where possible) that switch statements in plat comply with MISRA rules 16.1 - 16.7. Change-Id: Ie4a7d2fd10f6141c0cfb89317ea28a755391622f Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
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- 02 Feb, 2018 2 commits
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Masahiro Yamada authored
Looks like this is requirement in the pre-merge static analysis. misra_violation: [Required] MISRA C-2012 Rule 7.2 violation: Unsigned constants must be declared with U or u suffix. Adding ULL as requested. I used ULL() macros for BL*_{BASE,LIMIT} because they are referenced from linker scripts. Requested-by: David Cunado <david.cunado@arm.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Currently, the xlat region of the on-chip SRAM is always allocated for all BL images. The access to the on-chip SRAM is necessary for loading images from a USB memory device (i.e. when updating firmware), so unneeded for the usual boot procedure. To avoid this waste, allocate the xlat region dynamically only for BL2, and only when it is necessary. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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