- 15 Mar, 2018 4 commits
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Rajan Vaja authored
Implement ioctl APIs which uses MMIO operations to control RPU operations. Below IOCTLs are supported in this patch: * Get RPU operation mode * Set RPU operation mode * Configure RPU boot address (OCM/TCM) * Configure TCM combined mode Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Rajan Vaja authored
Implement pin control APIs which uses MMIO operations to set/get functions for the given pin. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Rajan Vaja authored
Add wrappers for pin control APIs. Actual implementation of these APIs would be done in subsequent changes. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Rajan Vaja authored
Add new function and node IDs supported by PMUFW in function list and node list respectively. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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- 03 May, 2017 1 commit
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dp-arm authored
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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- 16 Nov, 2016 1 commit
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Soren Brinkmann authored
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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- 13 Sep, 2016 7 commits
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Siva Durga Prasad Paladugu authored
Add support to provide silicon id to non-secure software through SMC. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> [ sb Move zynqmp_get_silicon_id outside of compile guards to avoid build errors. ] Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
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Nava kishore Manne authored
This patch adds pm_fpga_load() and pm_fpga_get_status() API's to provide the Access to the xilfpga library to load the bitstream into zynqmp PL region. Signed-off-by: Nava kishore Manne <navam@xilinx.com>
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Nava kishore Manne authored
This patch adds a new pm ID to sync with PMUFW ID numbers. Signed-off-by: Nava kishore Manne <navam@xilinx.com>
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Filip Drazic authored
During system suspend, identify slaves which are configured as wake sources and call pm_set_wakeup_source API for each of them. Identifying if device may wake the system is done by checking if any interrupt of that device is enabled in GICD_ISENABLER when the APU is about to enter SUSPEND_TO_RAM state. If such interrupt is found, pm_set_wakeup_source is called with corresponding PM node ID as argument. Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
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Filip Drazic authored
Signed-off-by: Filip Drazic <filip.drazic@aggios.com>
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Filip Drazic authored
The state argument of the pm_self_suspend API encodes the state to which the APU intends to suspend. The state can be: - PM_APU_STATE_CPU_IDLE - processor power down, all memories remain on - PM_APU_STATE_SUSPEND_TO_RAM - all processors powered down, L2$ powered down, all OCM banks in retention and DDR in self-refresh. The calls for setting requirements for L2$ and OCM banks are now redundant and removed. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> [ sb - remove redundant #defines ] Signed-off-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
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Mirela Simonovic authored
Nodes represent IPI dedicated to the RPU (not accessible by APU) Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
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- 07 Jun, 2016 1 commit
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Mirela Simonovic authored
NODE_IPI_APU is the node ID of APU's IPI device. If APU should be woken-up on an IPI from FPD power down, this node shall be set as the wake-up source upon suspend. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
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- 24 May, 2016 1 commit
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Anes Hadziahmetagic authored
Signed-off-by: Anes Hadziahmetagic <anes.hadziahmetagic@aggios.com> Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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- 06 Apr, 2016 1 commit
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Soren Brinkmann authored
The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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