1. 29 Mar, 2021 1 commit
    • Aditya Angadi's avatar
      board/rdv1mc: initialize tzc400 controllers · f97b5795
      Aditya Angadi authored
      
      
      A TZC400 controller is placed inline on DRAM channels and regulates
      the secure and non-secure accesses to both secure and non-secure
      regions of the DRAM memory. Configure each of the TZC controllers
      across the Chips.
      
      For use by secure software, configure the first chip's trustzone
      controller to protect the upper 16MB of the memory of the first DRAM
      block for secure accesses only. The other regions are configured for
      non-secure read write access. For all the remote chips, all the DRAM
      regions are allowed for non-secure read and write access.
      Signed-off-by: default avatarAditya Angadi <aditya.angadi@arm.com>
      Change-Id: I809f27eccadfc23ea0ef64e2fd87f95eb8f195c1
      f97b5795
  2. 11 Jan, 2021 1 commit
  3. 09 Dec, 2020 1 commit
  4. 05 Oct, 2020 1 commit
  5. 02 Sep, 2020 1 commit
  6. 21 Jul, 2020 1 commit
  7. 24 Jun, 2020 1 commit
    • Manish V Badarkhe's avatar
      plat/arm: Rentroduce tb_fw_config device tree · 3cb84a54
      Manish V Badarkhe authored
      
      
      Moved BL2 configuration nodes from fw_config to newly
      created tb_fw_config device tree.
      
      fw_config device tree's main usage is to hold properties shared
      across all BLx images.
      An example is the "dtb-registry" node, which contains the
      information about the other device tree configurations
      (load-address, size).
      
      Also, Updated load-address of tb_fw_config which is now located
      after fw_config in SRAM.
      Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      Change-Id: Ic398c86a4d822dacd55b5e25fd41d4fe3888d79a
      3cb84a54
  8. 23 Apr, 2020 1 commit