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  1. 18 Aug, 2020 1 commit
  3. 14 Aug, 2020 1 commit
    • Jimmy Brisson's avatar
      Prevent colliding identifiers · d74c6b83
      Jimmy Brisson authored 
      

There was a collision between the name of the typedef in the CASSERT and
something else, so we make the name of the typedef unique to the
invocation of DEFFINE_SVC_UUID2 by appending the name that's passed into
the macro. This eliminates the following MISRA violation:

    bl1/bl1_main.c:233:[MISRA C-2012 Rule 5.6 (required)] Identifier
    "invalid_svc_uuid" is already used to represent a typedef.

This also resolves MISRA rule 5.9.

These renamings are as follows:
  * tzram -> secram. This matches the function call name as it has
  sec_mem in it's  name
  * fw_config_base -> config_base. This file does not mess with
  hw_conig, so there's little chance of confusion

Change-Id: I8734ba0956140c8e29b89d0596d10d61a6ef351e
Signed-off-by: default avatarJimmy Brisson <jimmy.brisson@arm.com>
      d74c6b83
  5. 10 Aug, 2020 1 commit
    • Alexei Fedorov's avatar
      TF-A AMU extension: fix detection of group 1 counters. · f3ccf036
      Alexei Fedorov authored 
      

This patch fixes the bug when AMUv1 group1 counters was
always assumed being implemented without checking for its
presence which was causing exception otherwise.
The AMU extension code was also modified as listed below:
- Added detection of AMUv1 for ARMv8.6
- 'PLAT_AMU_GROUP1_NR_COUNTERS' build option is removed and
number of group1 counters 'AMU_GROUP1_NR_COUNTERS' is now
calculated based on 'AMU_GROUP1_COUNTERS_MASK' value
- Added bit fields definitions and access functions for
AMCFGR_EL0/AMCFGR and AMCGCR_EL0/AMCGCR registers
- Unification of amu.c Aarch64 and Aarch32 source files
- Bug fixes and TF-A coding style compliant changes.

Change-Id: I14e407be62c3026ebc674ec7045e240ccb71e1fb
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      f3ccf036
  7. 09 Aug, 2020 1 commit
  9. 23 Jul, 2020 3 commits
  11. 21 Jul, 2020 1 commit
  13. 14 Jul, 2020 1 commit
    • Alexei Fedorov's avatar
      TF-A: Redefine true/false definitions · 0aa9f3c0
      Alexei Fedorov authored 
      

This patch redefines 'true' and 'false' definitions in
'include/lib/libc/stdbool.h' to fix defect reported by
MISRA C-2012 Rule 10.1
"The expression \"0\" of non-boolean essential type is
being interpreted as a boolean value for the operator \"? :\"."

Change-Id: Ie1b16e5826e5427cc272bd753e15d4d283e1ee4c
Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      0aa9f3c0
  15. 27 Jun, 2020 1 commit
  17. 25 Jun, 2020 3 commits
  19. 24 Jun, 2020 2 commits
  21. 22 Jun, 2020 2 commits
  23. 12 Jun, 2020 1 commit
  25. 02 Jun, 2020 1 commit
    • Masahisa Kojima's avatar
      xlat_tables_v2: add base table section name parameter for spm_mm · 0922e481
      Masahisa Kojima authored 
      Core spm_mm code expects the translation tables are located in the
inner & outer WBWA & shareable memory.
REGISTER_XLAT_CONTEXT2 macro is used to specify the translation
table section in spm_mm.

In the commit 363830df

 (xlat_tables_v2: merge
REGISTER_XLAT_CONTEXT_{FULL_SPEC,RO_BASE_TABLE}), REGISTER_XLAT_CONTEXT2
macro explicitly specifies the base xlat table goes into .bss by default.
This change affects the existing SynQuacer spm_mm implementation.
plat/socionext/synquacer/include/plat.ld.S linker script intends to
locate ".bss.sp_base_xlat_table" into "sp_xlat_table" section,
but this implementation is no longer available.

This patch adds the base table section name parameter for
REGISTER_XLAT_CONTEXT2 so that platform can specify the
inner & outer WBWA & shareable memory for spm_mm base xlat table.
If PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME is not defined, base xlat table
goes into .bss by default, the result is same as before.

Change-Id: Ie0e1a235e5bd4288dc376f582d6c44c5df6d31b2
Signed-off-by: default avatarMasahisa Kojima <masahisa.kojima@linaro.org>
      0922e481
  27. 01 Jun, 2020 2 commits
  29. 19 May, 2020 2 commits
    • johpow01's avatar
      Enable v8.6 WFE trap delays · 6cac724d
      johpow01 authored 
      

This patch enables the v8.6 extension to add a delay before WFE traps
are taken. A weak hook plat_arm_set_twedel_scr_el3 has been added in
plat/common/aarch64/plat_common.c that disables this feature by default
but platform-specific code can override it when needed.

The only hook provided sets the TWED fields in SCR_EL3, there are similar
fields in HCR_EL2, SCTLR_EL2, and SCTLR_EL1 to control WFE trap delays in
lower ELs but these should be configured by code running at EL2 and/or EL1
depending on the platform configuration and is outside the scope of TF-A.
Signed-off-by: default avatarJohn Powell <john.powell@arm.com>
Change-Id: I0a9bb814205efeab693a3d0a0623e62144abba2d
      6cac724d
    • Max Shvetsov's avatar
      Fix exception in save/restore of EL2 registers. · 30ee3755
      Max Shvetsov authored 
      

Removing FPEXC32_EL2 from the register save/restore routine for EL2
registers since it is already a part of save/restore routine for
fpregs.
Signed-off-by: default avatarMax Shvetsov <maksims.svecovs@arm.com>
Change-Id: I5ed45fdbf7c8efa8dcfcd96586328d4f6b256bc4
      30ee3755
  31. 07 Apr, 2020 1 commit
    • Julius Werner's avatar
      coreboot: Add memory range parsing · 579d1e90
      Julius Werner authored 
      

This patch adds code to parse memory range information passed by
coreboot, and a simple helper to test whether a specific address belongs
to a range. This may be useful for coreboot-using platforms that need to
know information about the system's memory layout (e.g. to check whether
an address passed in via SMC targets valid DRAM).
Signed-off-by: default avatarJulius Werner <jwerner@chromium.org>
Change-Id: I3bea326c426db27d1a8b7d6e17418e4850e884b4
      579d1e90
  33. 03 Apr, 2020 2 commits
    • John Powell's avatar
      Fix MISRA C issues in BL1/BL2/BL31 · 3443a702
      John Powell authored 
      

Attempts to address MISRA compliance issues in BL1, BL2, and BL31 code.
Mainly issues like not using boolean expressions in conditionals,
conflicting variable names, ignoring return values without (void), adding
explicit casts, etc.

Change-Id: If1fa18ab621b9c374db73fa6eaa6f6e5e55c146a
Signed-off-by: default avatarJohn Powell <john.powell@arm.com>
      3443a702
    • Pramod Kumar's avatar
      xlat lib v2: Add support to pass shareability attribute for normal memory region · 06aca857
      Pramod Kumar authored 
      

Present framework restricts platform to pass desired shareability attribute
for normal memory region mapped in MMU. it defaults to inner shareability.

There are platforms where memories (like SRAM) are not placed at snoopable
region in advaned interconnect like CCN/CMN hence snoopable transaction is
not possible to these memory. Though These memories could be mapped in MMU
as MT_NON_CACHEABLE, data caches benefits won't be available.

If these memories are mapped as cacheable with non-shareable attribute,
when only one core is running like at boot time, MMU data cached could be
used for faster execution. Hence adding support to pass the shareability
attribute for memory regions.
Signed-off-by: default avatarPramod Kumar <pramod.kumar@broadcom.com>
Change-Id: I678cb50120a28dae4aa9d1896e8faf1dd5cf1754
      06aca857
  35. 02 Apr, 2020 3 commits
    • Sandrine Bailleux's avatar
      Check for out-of-bound accesses in the CoT description · 6f8a2565
      Sandrine Bailleux authored 
      

The chain of trust array is now always accessed through a fconf getter.
This gives us an ideal spot to check for out-of-bound accesses.

Change-Id: Ic5ea20e43cf8ca959bb7f9b60de7c0839b390add
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      6f8a2565
    • Masahiro Yamada's avatar
      Pass more -D options to BL*_CPPFLAGS instead of BL*_CFLAGS · 9cefb4b1
      Masahiro Yamada authored 
      Commit d5e97a1d ("Build: define IMAGE_AT_EL1 or IMAGE_AT_EL3
globally for C files") does not have commit 848a7e8c ("Build:
introduce per-BL CPPFLAGS and ASFLAGS") as an ancestor because
they were pulled almost at the same time.

This is a follow-up conversion to be consistent with commit
11a3c5ee

 ("plat: pass -D option to BL*_CPPFLAGS instead of
BL*_CFLAGS").

With this change, the command line option, IMAGE_AT_EL3, will be
passed to .S files as well.

I remove the definition in include/lib/cpus/aarch64/cpu_macros.S

Otherwise, the following error would happen.

  include/lib/cpus/aarch64/cpu_macros.S:29:0: error: "IMAGE_AT_EL3" redefined [-Werror]

Change-Id: I943c8f22356483c2ae3c57b515c69243a8fa6889
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      9cefb4b1
    • Masahiro Yamada's avatar
      xlat_tables_v2: fix assembler warning of PLAT_RO_XLAT_TABLES · 268131c2
      Masahiro Yamada authored 
      

If PLAT_RO_XLAT_TABLES is defined, the base xlat table goes to the
.rodata section instead of .bss section.

This causes a warning like:

/tmp/ccswitLr.s: Assembler messages:
/tmp/ccswitLr.s:297: Warning: setting incorrect section attributes for .rodata

It is practically no problem, but I want to keep the build log clean.

Put the base table into the "base_xlat_table" section to suppress the
assembler warnings.

The linker script determines its final destination; rodata section if
PLAT_RO_XLAT_TABLES=1, or bss section otherwise. So, the result is the
same.

Change-Id: Ic85d1d2dddd9b5339289fc2378cbcb21dd7db02e
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      268131c2
  37. 01 Apr, 2020 1 commit
    • Varun Wadekar's avatar
      include: fixup 'cm_setup_context' prototype · 25d819a3
      Varun Wadekar authored 
      

This patch changes the prototype cm_setup_context() to use struct entry_point_info
rather than the typedef'ed version of it. This fixes the following compilation error
seen with EL3_EXCEPTION_HANDLING = 1.

<snip>
In file included from bl31/ehf.c:19:
include/lib/el3_runtime/context_mgmt.h:35:49: error: unknown type name 'entry_point_info_t'
   35 | void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep);
      |                                                 ^~~~~~~~~~~~~~~~~~
<snip>
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
Change-Id: I73b059ff2dade2259cefd0f9a097c7ea4a88055d
      25d819a3
  39. 31 Mar, 2020 1 commit
  41. 25 Mar, 2020 1 commit
    • Manish V Badarkhe's avatar
      Fix 'tautological-constant-compare' error · 4c4a1327
      Manish V Badarkhe authored 
      

Fixed below 'tautological-constant-compare' error when building the source
code with latest clang compiler <clang version 11.0.0>.

plat/common/plat_psci_common.c:36:2:
error: converting the result of '<<' to a boolean always evaluates
to true [-Werror,-Wtautological-constant-compare]
        PMF_STORE_ENABLE)
        ^
include/lib/pmf/pmf.h:28:29: note: expanded from macro 'PMF_STORE_ENABLE'
PMF_STORE_ENABLE        (1 << 0)

This error is observed beacuse of CASSERT placed in
"PMF_DEFINE_CAPTURE_TIMESTAMP" which do below stuff:
CASSERT(_flags, select_proper_config);
where _flags = PMF_STORE_ENABLE (1 << 0) which always results true.
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ifa82ea202496a23fdf1d27ea1798d1f1b583a021
      4c4a1327
  43. 20 Mar, 2020 1 commit
  45. 19 Mar, 2020 1 commit
  47. 11 Mar, 2020 3 commits
    • Madhukar Pappireddy's avatar
      fconf: enhancements to firmware configuration framework · 25d740c4
      Madhukar Pappireddy authored 
      

A populate() function essentially captures the value of a property,
defined by a platform, into a fconf related c structure. Such a
callback is usually platform specific and is associated to a specific
configuration source.
For example, a populate() function which captures the hardware topology
of the platform can only parse HW_CONFIG DTB. Hence each populator
function must be registered with a specific 'config_type' identifier.
It broadly represents a logical grouping of configuration properties
which is usually a device tree source file.

Example:
> TB_FW: properties related to trusted firmware such as IO policies,
	 base address of other DTBs, mbedtls heap info etc.
> HW_CONFIG: properties related to hardware configuration of the SoC
	 such as topology, GIC controller, PSCI hooks, CPU ID etc.

This patch modifies FCONF_REGISTER_POPULATOR macro and fconf_populate()
to register and invoke the appropriate callbacks selectively based on
configuration type.

Change-Id: I6f63b1fd7a8729c6c9137d5b63270af1857bb44a
Signed-off-by: default avatarMadhukar Pappireddy <madhukar.pappireddy@arm.com>
      25d740c4
    • Masahiro Yamada's avatar
      xlat_tables_v2: use ARRAY_SIZE in REGISTER_XLAT_CONTEXT_FULL_SPEC · e2822458
      Masahiro Yamada authored 
      

With this, it is clearer that .base_table_entries and .tables_num
are the array size of .base_table and .tables, respectively.

Change-Id: I634e65aba835ab9908cc3919355df6bc6e18d42a
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      e2822458
    • Masahiro Yamada's avatar
      xlat_tables_v2: merge REGISTER_XLAT_CONTEXT_{FULL_SPEC,RO_BASE_TABLE} · 363830df
      Masahiro Yamada authored 
      

xlat_tables_v2_helpers.h defines two quite similar macros,
REGISTER_XLAT_CONTEXT_FULL_SPEC and REGISTER_XLAT_CONTEXT_RO_BASE_TABLE.

Only the difference is the section of _ctx_name##_base_xlat_table.

Parameterize it and unify these two macros.

The base xlat table goes into the .bss section by default.
If PLAT_RO_XLAT_TABLES is defined, it goes into the .rodata section.

Change-Id: I8b02f4da98f0c272e348a200cebd89f479099c55
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      363830df
  49. 03 Mar, 2020 1 commit
    • Max Shvetsov's avatar
      SPMD: Adds partially supported EL2 registers. · 2825946e
      Max Shvetsov authored 
      

This patch adds EL2 registers that are supported up to ARMv8.6.
ARM_ARCH_MINOR has to specified to enable save/restore routine.

Note: Following registers are still not covered in save/restore.
 * AMEVCNTVOFF0<n>_EL2
 * AMEVCNTVOFF1<n>_EL2
 * ICH_AP0R<n>_EL2
 * ICH_AP1R<n>_EL2
 * ICH_LR<n>_EL2

Change-Id: I4813f3243e56e21cb297b31ef549a4b38d4876e1
Signed-off-by: default avatarMax Shvetsov <maksims.svecovs@arm.com>
      2825946e
  51. 02 Mar, 2020 1 commit
  53. 27 Feb, 2020 1 commit
    • Louis Mayencourt's avatar
      fconf: Fix misra issues · 845db722
      Louis Mayencourt authored 
      

MISRA C-2012 Rule 20.7:
Macro parameter expands into an expression without being wrapped by parentheses.

MISRA C-2012 Rule 12.1:
Missing explicit parentheses on sub-expression.

MISRA C-2012 Rule 18.4:
Essential type of the left hand operand is not the same as that of the right
operand.

Include does not provide any needed symbols.

Change-Id: Ie1c6451cfbc8f519146c28b2cf15c50b1f36adc8
Signed-off-by: default avatarLouis Mayencourt <louis.mayencourt@arm.com>
      845db722