Skip to content

GitLab

Switch branch/tag
  1. 16 Oct, 2020 1 commit
    • Pali Rohár's avatar
      plat: marvell: armada: Fix dependences for target fip · fb28d525
      Pali Rohár authored 
      

For building fip image it is not needed to build target mrvl_flash. This
fip image contains only bl2, bl31 and bl33 (u-boot.bin) images and
therefore it does not depend on Marvell wtmi and wtp A3700-utils.

So remove mrvl_flash dependency for fip target to allow building fip image
without need to build mrvl_flash and therefore specify and provide Marvell
wmi and wtp A3700-utils.

This changes fixes compilation of fip image for A3700 platform by command:

    make CROSS_COMPILE=aarch64-linux-gnu- BL33=/path/u-boot/u-boot.bin \
         DEBUG=0 LOG_LEVEL=0 USE_COHERENT_MEM=0 PLAT=a3700 fip

Marvell boot image can be still build by 'mrvl_flash' target.
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: Iba9a9da5be6fd1da23407fc2d490aedcb1a292c9
      fb28d525
  3. 04 Oct, 2020 5 commits
  5. 04 Aug, 2020 1 commit
    • Grant Likely's avatar
      Use abspath to dereference $BUILD_BASE · 29214e95
      Grant Likely authored 
      

If the user tries to change BUILD_BASE to put the build products outside
the build tree the compile will fail due to hard coded assumptions that
$BUILD_BASE is a relative path. Fix by using $(abspath $(BUILD_BASE))
to rationalize to an absolute path every time and remove the relative
path assumptions.

This patch also adds documentation that BUILD_BASE can be specified by
the user.
Signed-off-by: default avatarGrant Likely <grant.likely@arm.com>
Signed-off-by: default avatarManish Pandey <manish.pandey2@arm.com>
Change-Id: Ib1af874de658484aaffc672f30029b852d2489c8
      29214e95
  7. 30 Jul, 2020 6 commits
    • Grzegorz Jaszczyk's avatar
      plat: marvell: octeontx: add support for t9130 · 2c9d2636
      Grzegorz Jaszczyk authored 
      

CN-9130 has single CP0 inside the package and 2 additional one from MoChi
interface. In case of db-9130-modular board the MCI interface is routed to:
- on-board CP115 (MCI0)
- extension board CP115 (MCI1)

The board is based on DIMM DDR.

The 9130 has up to 3CP, and decoding windows looks like below:

  (free for further use)
 .----------. 0xf800 0000
 | CP2 CFG  |
 '----------' 0xf600 0000
 | CP1 CFG  |
 '----------' 0xf400 0000
 | CP0 CFG  |
 '----------' 0xf200 0000
 | AP CFG   |
 '----------' 0xf000 0000
  (free for further use)
 .----------. 0xec00 0000
 | SPI      |
 | MEM_MAP  | (Currently not opened)
 '----------' 0xe800 0000
 | PEX2_CP2 |
 '----------' 0xe700 0000
 | PEX1_CP2 |
 '----------' 0xe600 0000
 | PEX0-CP2 |
 '----------'
 .----------. 0xe500 0000
 | PEX2_CP1 |
 '----------' 0xe400 0000
 | PEX1_CP1 |
 '----------' 0xe300 0000
 | PEX0-CP1 |
 '----------'
 .----------. 0xe200 0000
 | PEX2-CP0 |
 '----------' 0xe100 0000
 | PEX1-CP0 |
 '----------' 0xe000 0000
 | PEX0-CP0 |
 | 512MB    |
 '----------' 0xc000 0000

Change-Id: Ia8eee4f96c1043753f74f9da437b9f72ce2d6eb0
Signed-off-by: default avatarGrzegorz Jaszczyk <jaz@semihalf.com>
      2c9d2636
    • Alex Evraev's avatar
      plat: marvell: t9130: add SVC support · 12c66c6b
      Alex Evraev authored 
      

As the preparation for adding the CN913x SoC family support
introduce code that enable SVC and the frequency handling
specific for the AP807 North Bridge.

Change-Id: Ibe34a511b49cd9671a2e53b77bdcfc644bb915e3
Signed-off-by: default avatarAlex Evraev <alexev@marvell.com>
      12c66c6b
    • Grzegorz Jaszczyk's avatar
      plat: marvell: t9130: update AVS settings · 885cd821
      Grzegorz Jaszczyk authored 
      

Update AVS settings and remove unused macros.
This is a preparation patch for adding CN913x SoC
family support.

Change-Id: Ib1dd70885a316ed5763d0f4730d0e4734da117b7
Signed-off-by: default avatarGrzegorz Jaszczyk <jaz@semihalf.com>
      885cd821
    • Ben Peled's avatar
      plat: marvell: t9130: pass actual CP count for load_image · 5bc3643e
      Ben Peled authored 
      

Add CN913x case to bl2_plat_get_cp_count.
Fix loading of cp1/2 image. This is a preparation
patch for adding CN913x SoC family support.

Change-Id: Id84a30203d20572fc0dfd3f91ea395c199a85fe9
Signed-off-by: default avatarBen Peled <bpeled@marvell.com>
      5bc3643e
    • Alex Evraev's avatar
      plat: marvell: armada: a7k: add support to SVC validation mode · ebf307bf
      Alex Evraev authored 
      

Add support for “AVS reduction” feature at this mode for
7040 Dual Cluster operation mode at CPU=1600MHz

Change-Id: Ia72b10e0ccfad07568bf4c089ea3990173ae24b2
Signed-off-by: default avatarAlex Evraev <alexev@marvell.com>
      ebf307bf
    • Moti Buskila's avatar
      plat: marvell: armada: add support for twin-die combined memory device · 48270689
      Moti Buskila authored 
      

the twin-die combined memory device should be treated as
X8 device and not as X16 one. This patch is required to
re-enable compilation after BLE (mv-ddr-marvell) firmware upgrade.

Change-Id: I41257ff2825164ebca85a84bbb8462d7b3447b97
Signed-off-by: default avatarMoti Buskila <motib@marvell.com>
Signed-off-by: default avatarMarcin Wojtas <mw@semihalf.com>
      48270689
  9. 10 Jul, 2020 6 commits
  11. 03 Jul, 2020 2 commits
  13. 19 Jun, 2020 11 commits
  15. 18 Jun, 2020 1 commit
    • Marcin Wojtas's avatar
      plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs · b5c850d4
      Marcin Wojtas authored 
      

The Marvell Armada 37xx SoCs-based platforms contain a bit
awkward directory structure because the currently only one
supported PLAT and PLAT_FAMILY are the same. Modify the latter
to 'a3k' in order to improve it and keep plat/marvell/armada
tree more consistent:

plat/marvell/
├── armada
│   ├── a3k
│   │   ├── a3700

[...]

│   ├── a8k
│   │   ├── a70x0

[...]

Change-Id: I693a6ef88e6ce49a326a3328875c90bbc186066a
Signed-off-by: default avatarMarcin Wojtas <mw@semihalf.com>
      b5c850d4
  17. 06 Jun, 2020 7 commits