- 19 Aug, 2020 2 commits
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Jacky Bai authored
The number of gpc imr mask reg & the offset is different on some SOC, so correct it & replace the magic number with macro define. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Ic701675cdd92e043dcd7f06722f2e871068aec74
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Jacky Bai authored
Keep A53 PLAT(SCU) power domain on in wait mode(ret). RBC count only need to be set in PLAT OFF mode, so change it accordingly. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Ie55e25c8210d298506fc4dca7a9653583db45e0c
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- 18 Aug, 2020 6 commits
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David Pu authored
This patch adds tegra_chipid_is_t194() function to check if it is a Tegra 194 chip. Change-Id: I6da6d3a2c9676b748931e42fde1b174cbcb4fd40 Signed-off-by: David Pu <dpu@nvidia.com>
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David Pu authored
This patch makes Tegra platform psci ops routines to static. These routines are called by PSCI framework and no external linkage is necessary. This patch also fixes MISRA C-2012 Rule 8.6 violations. Change-Id: Idd2381809f76dc0fd578c1c92c0f8eea124f2e88 Signed-off-by: David Pu <dpu@nvidia.com>
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Masahisa Kojima authored
Enable the spm_mm framework for the qemu_sbsa platform. Memory layout required for spm_mm is created in secure SRAM. Co-developed-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I104a623e8bc1e44d035b95f014a13b3f8b33a62a
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Manish V Badarkhe authored
Implemented platform functions to retrieve the soc-id information for juno platform Change-Id: Ie677120710b45e202a2d63a954459ece8a64b353 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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Manish V Badarkhe authored
Implemented platform functions to retrieve the soc-id information for FVP platform. Change-Id: Id3df02ab290a210310e8d34ec9d706a59d817517 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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Manish V Badarkhe authored
Removed common code for soc-id feature which is applicable for all arm platforms. In subsequent patches, added a platform based functions for FVP and Juno to retrieve the soc-id information. Change-Id: Idb632a935758a6caff2ca03a6eab8f663da8a93a Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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- 17 Aug, 2020 1 commit
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Madhukar Pappireddy authored
SP804 TIMER is not platform specific, and current code base adds multiple defines to use this driver. Like FVP_USE_SP804_TIMER and FVP_VE_USE_SP804_TIMER. This patch removes platform specific build flag and adds generic flag `USE_SP804_TIMER` to be set to 1 by platform if needed. Change-Id: I5ab792c189885fd1b98ddd187f3a38ebdd0baba2 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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- 14 Aug, 2020 5 commits
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Yann Gautier authored
Include the GICv2 makefile in STM32MP1 SP_min makefile, and use ${GICV2_SOURCES} instead of taking drivers/arm/gic files directly. Change-Id: Ibcaed5b0bd17f6d8cf200e208c11cc10cd6d2ee5 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Ruari Phipps authored
For supporting dualroot CoT for Secure Partitions a new optional field "owner" is introduced which will be used to sign the SP with corresponding signing domain. To demonstrate its usage, this patch adds owners to cactus Secure Partitions. Signed-off-by: Ruari Phipps <ruari.phipps@arm.com> Change-Id: I7b760580355fc92edf5402cecc38c38125dc1cae
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Manish Pandey authored
For Arm platforms SPs are loaded by parsing tb_fw_config.dts and adding them to SP structure sequentially, which in-turn is appended to loadable image list. With recently introduced dualroot CoT for SPs where they are owned either by SiP or by Platform. SiP owned SPs index starts at SP_PKG1_ID and Plat owned SPs index starts at SP_PKG5_ID. As the start index of SP depends on the owner, there should be a mechanism to parse owner of a SP and put it at the correct index in SP structure. This patch adds support for parsing a new optional field "owner" and based on it put SP details(UUID & Load-address) at the correct index in SP structure. Change-Id: Ibd255b60d5c45023cc7fdb10971bef6626cb560b Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
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Jimmy Brisson authored
This resolves MISRA defects such as: plat/common/plat_bl1_common.c:63:[MISRA C-2012 Rule 14.4 (required)] The condition expression "1" does not have an essentially boolean type. Change-Id: I679411980ad661191fbc834a44a5eca5494fd0e2 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
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Jimmy Brisson authored
There was a collision between the name of the typedef in the CASSERT and something else, so we make the name of the typedef unique to the invocation of DEFFINE_SVC_UUID2 by appending the name that's passed into the macro. This eliminates the following MISRA violation: bl1/bl1_main.c:233:[MISRA C-2012 Rule 5.6 (required)] Identifier "invalid_svc_uuid" is already used to represent a typedef. This also resolves MISRA rule 5.9. These renamings are as follows: * tzram -> secram. This matches the function call name as it has sec_mem in it's name * fw_config_base -> config_base. This file does not mess with hw_conig, so there's little chance of confusion Change-Id: I8734ba0956140c8e29b89d0596d10d61a6ef351e Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
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- 13 Aug, 2020 1 commit
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Saurabh Gorecha authored
This patch adds RNG driver and use it to generate random number for stack protection. Change-Id: I73d79e68d08b5aa902dc7fad48e17a03f996178d Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
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- 10 Aug, 2020 2 commits
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Alexei Fedorov authored
BL31 binary size is aligned to 4KB because of the code in include\plat\arm\common\arm_reclaim_init.ld.S: __INIT_CODE_UNALIGNED__ = .; . = ALIGN(PAGE_SIZE); __INIT_CODE_END__ = .; with all the zero data after the last instruction of BL31 code to the end of the page. This causes increase in size of BL31 binary stored in FIP and its loading time by BL2. This patch reduces the size of BL31 image by moving page alignment from __INIT_CODE_END__ to __STACKS_END__ which also increases the stack size for secondary CPUs. Change-Id: Ie2ec503fc774c22c12ec506d74fd3ef2b0b183a9 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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Saurabh Gorecha authored
Adding support for QTI CHIP SC7180 on ATF Change-Id: I0d82d3a378036003fbd0bc4784f61464bb76ea82 Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org> Co-authored-by: Maulik Shah <mkshah@codeaurora.org>
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- 09 Aug, 2020 2 commits
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Varun Wadekar authored
This patch removes the unused TZRAM setup function from the memory controller driver. Change-Id: Ic16f21fb84c47df71be6ab3e1e286640daa39291 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch moves the 'drivers' and the 'lib' folders out of the 'common' folder. This way the 'common' folder shall contain only the platform support required for all Tegra platforms. Change-Id: I2f238572d0a078d60c6b458a559538dc8a4d1856 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 06 Aug, 2020 1 commit
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Peng Fan authored
Add sdei support for i.MX8MM, this is to let jailhouse Hypervisor could use SDEI to do hypervisor management, after physical IRQ has been disabled routing. Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: I5fd697fee22df151e13d0f1335e8ac8a7bae6189
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- 04 Aug, 2020 1 commit
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Grant Likely authored
If the user tries to change BUILD_BASE to put the build products outside the build tree the compile will fail due to hard coded assumptions that $BUILD_BASE is a relative path. Fix by using $(abspath $(BUILD_BASE)) to rationalize to an absolute path every time and remove the relative path assumptions. This patch also adds documentation that BUILD_BASE can be specified by the user. Signed-off-by: Grant Likely <grant.likely@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib1af874de658484aaffc672f30029b852d2489c8
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- 31 Jul, 2020 4 commits
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Alexei Fedorov authored
This patch fixes BL31 linker error "relocation R_AARCH64_ABS32 against `a local symbol' can not be used when making a shared object" when Position Independent Executable (PIE) support is enabled with ENABLE_PIE=1 build option. Change-Id: I2692269676db3f3b27eed499fc029fffb67969be Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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Manish Pandey authored
Currently only single signing domain is supported for SP packages but there is plan to support dual signing domains if CoT is dualroot. SP_CONTENT_CERT_ID is the certificate file which is currently generated and signed with trusted world key which in-turn is derived from Silicon provider RoT key. To allow dual signing domain for SP packages, other certificate file will be derived from Platform owned RoT key. This patch renames "SP_CONTENT_CERT_ID" to "SIP_SP_CONTENT_CERT_ID" and does other related changes. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I0bc445a3ab257e2dac03faa64f46e36a9fed5e93
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Olivier Deprez authored
Following merge of patchset [1] the spm_mm_boot_info_t structure is included in few platform files unconditionally even when SPM_MM option is disabled. [1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/2647 Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I68bc034c9348b5d9bcfd2e5217b781df5ad1b369
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Nina Wu authored
- Add basic platform setup - Add mt8192 documentation at docs/plat/ - Add generic CPU helper functions - Add basic register address Change-Id: Ife34622105404a8227441aab939e3c55c96374e9 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
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- 30 Jul, 2020 10 commits
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Andre Przywara authored
The command line for BL33 payloads is typically taken from the DTB. On "normal" systems the bootloader will put the right version in there, but we typically don't use one on the FPGAs. To avoid editing (and possibly re-packaging) the DTB for every change in the command line, try to read it from some "magic" memory location instead. It can be easily placed there by the tool that uploads the other payloads to the FPGA's memory. BL31 will then replace the existing command line in the DTB with that new string. To avoid reading garbage, check the memory location for containing a magic value. This is conveniently chosen to be a simple ASCII string, so it can just preceed the actual command line in a text file: -------------------------------- CMD:console=ttyAMA0,38400n8 debug loglevel=8 -------------------------------- Change-Id: I5923a80332c9fac3b4afd1a6aaa321233d0f60da Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Olivier Deprez authored
Provide manifest and build options to boot OP-TEE as a guest S-EL1 Secure Partition on top of Hafnium in S-EL2. Increase ARM_SP_MAX_SIZE to cope with OP-TEE debug build image. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Idd2686fa689a78fe2d05ed92b1d23c65e2edd4cb
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Grzegorz Jaszczyk authored
CN-9130 has single CP0 inside the package and 2 additional one from MoChi interface. In case of db-9130-modular board the MCI interface is routed to: - on-board CP115 (MCI0) - extension board CP115 (MCI1) The board is based on DIMM DDR. The 9130 has up to 3CP, and decoding windows looks like below: (free for further use) .----------. 0xf800 0000 | CP2 CFG | '----------' 0xf600 0000 | CP1 CFG | '----------' 0xf400 0000 | CP0 CFG | '----------' 0xf200 0000 | AP CFG | '----------' 0xf000 0000 (free for further use) .----------. 0xec00 0000 | SPI | | MEM_MAP | (Currently not opened) '----------' 0xe800 0000 | PEX2_CP2 | '----------' 0xe700 0000 | PEX1_CP2 | '----------' 0xe600 0000 | PEX0-CP2 | '----------' .----------. 0xe500 0000 | PEX2_CP1 | '----------' 0xe400 0000 | PEX1_CP1 | '----------' 0xe300 0000 | PEX0-CP1 | '----------' .----------. 0xe200 0000 | PEX2-CP0 | '----------' 0xe100 0000 | PEX1-CP0 | '----------' 0xe000 0000 | PEX0-CP0 | | 512MB | '----------' 0xc000 0000 Change-Id: Ia8eee4f96c1043753f74f9da437b9f72ce2d6eb0 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Alex Evraev authored
As the preparation for adding the CN913x SoC family support introduce code that enable SVC and the frequency handling specific for the AP807 North Bridge. Change-Id: Ibe34a511b49cd9671a2e53b77bdcfc644bb915e3 Signed-off-by: Alex Evraev <alexev@marvell.com>
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Grzegorz Jaszczyk authored
Update AVS settings and remove unused macros. This is a preparation patch for adding CN913x SoC family support. Change-Id: Ib1dd70885a316ed5763d0f4730d0e4734da117b7 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Ben Peled authored
Add CN913x case to bl2_plat_get_cp_count. Fix loading of cp1/2 image. This is a preparation patch for adding CN913x SoC family support. Change-Id: Id84a30203d20572fc0dfd3f91ea395c199a85fe9 Signed-off-by: Ben Peled <bpeled@marvell.com>
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Alex Evraev authored
Add support for “AVS reduction” feature at this mode for 7040 Dual Cluster operation mode at CPU=1600MHz Change-Id: Ia72b10e0ccfad07568bf4c089ea3990173ae24b2 Signed-off-by: Alex Evraev <alexev@marvell.com>
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Moti Buskila authored
the twin-die combined memory device should be treated as X8 device and not as X16 one. This patch is required to re-enable compilation after BLE (mv-ddr-marvell) firmware upgrade. Change-Id: I41257ff2825164ebca85a84bbb8462d7b3447b97 Signed-off-by: Moti Buskila <motib@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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Andre Przywara authored
N1SDP supports both single-chip and multi-chip environment. Added DTS file for both type of environment. Enabled DTS files compilation for N1SDP platform. Change-Id: I66af88dcfb841893eb6ed2ca18d3025de81236a0 Co-authored-by: Robin Murphy <Robin.Murphy@arm.com> Co-authored-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com> Co-authored-by: Manoj Kumar <manoj.kumar3@arm.com> Co-authored-by: Anurag Koul <anurag.koul@arm.com> Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
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Manish Pandey authored
This patch fixes a bug where wrong panic was caused when the number of SP was same as max limit. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I9ace62d8d5bcdc410eeacdd9d33d55a7be5fcc8e
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- 26 Jul, 2020 3 commits
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Manish V Badarkhe authored
Enabled 'SMCCC_ARCH_SOC_ID' feature for Nvidia Tegra platforms. Change-Id: If17415f42304c6518aeead8dfe5909c378aaa777 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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Manish V Badarkhe authored
Currently, soc-revision information is not available for arm platforms hence disabled 'SMCCC_ARCH_SOC_ID' feature for all arm platforms. Change-Id: I1ab878c6a4c8fecfff63bc6dde83e3ecefe20279 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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Manish V Badarkhe authored
Currently, 'SMCCC_ARCH_FEATURES' SMC call handler unconditionally returns 'SMC_OK' for 'SMCCC_ARCH_SOC_ID' function. This seems to be not correct for the platform which doesn't implement soc-id functionality i.e. functions to retrieve both soc-version and soc-revision. Hence introduced a platform function which will check whether SMCCC feature is available for the platform. Also, updated porting guide for the newly added platform function. Change-Id: I389f0ef6b0837bb24c712aa995b7176117bc7961 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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- 24 Jul, 2020 2 commits
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Manish Pandey authored
SPM(BL32) and hafnium(BL33) expect their manifest base address in x0 register, which is updated during BL2 stage by parsing fw_config. In case of RESET_TO_BL31 it has to be updated while populating entry point information. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I6f4a97f3405029bd6ba25f0935e2d1f74bb95517
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Javier Almansa Sobrino authored
As secondary cores show up, they populate an array to announce themselves so plat_core_pos_by_mpidr() can return an invalid COREID code for any non-existing MPIDR that it is queried about. The Power Domain Tree Description is populated with a topology based on the maximum harcoded values. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I8fd64761a2296714ce0f37c46544f3e6f13b5f61
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