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  1. 13 Jan, 2021 2 commits
  3. 11 Jan, 2021 11 commits
  5. 23 Dec, 2020 1 commit
    • Pali Rohár's avatar
      marvell: uart: a3720: Implement console_a3700_core_flush · e63e4140
      Pali Rohár authored 
      

Implementation is simple, just wait for the TX FIFO to be empty.

Without this patch TF-A on A3720 truncate the last line:

  NOTICE:  BL31: Built : 16:1

With this patch TF-A on A3720 print correctly also the last line:

  NOTICE:  BL31: Built : 19:03:31, Dec 23 2020
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Change-Id: I2f2ea42beab66ba132afdb400ca7898c5419db09
      e63e4140
  7. 21 Dec, 2020 1 commit
  9. 08 Dec, 2020 1 commit
    • Marek Vasut's avatar
      rcar_gen3: drivers: console: Treat log as device memory · 60576747
      Marek Vasut authored 
      

The BL31 log driver is registered before the xlat tables are initialized,
at that point the log memory is configured as device memory and can only
be accessed with up-to-32bit aligned accesses. Adjust the driver to do
just that.

The memset() call has to be replaced by a loop of 32bit writes to the log,
the memcpy() is trivial to replace with a single 32bit write of the entire
TLOG word. In the end, this even simplifies the code.
Signed-off-by: default avatarMarek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie9152e782e67d93e7236069a294df812e2b873bf
      60576747
  11. 13 Oct, 2020 1 commit
  13. 12 Oct, 2020 3 commits
    • Jimmy Brisson's avatar
      Increase type widths to satisfy width requirements · d7b5f408
      Jimmy Brisson authored 
      

Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:

    bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
    The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
    0x3c0U" (32 bits) is less that the right hand operand
    "18446744073709547519ULL" (64 bits).

This also resolves MISRA defects such as:

    bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
    In the expression "3U << 20", shifting more than 7 bits, the number
    of bits in the essential type of the left expression, "3U", is
    not allowed.

Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.

This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,

    92407e73        and     x19, x19, #0xffffffff

from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.

The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.

Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16
Signed-off-by: default avatarJimmy Brisson <jimmy.brisson@arm.com>
      d7b5f408
    • Lionel Debieve's avatar
      drivers: stm32_fmc2_nand: fix boundary check for chip select · 495885bc
      Lionel Debieve authored 
      

Chip select is retrieved from device tree and check
must be done regarding the MAX_CS defined.
Signed-off-by: default avatarLionel Debieve <lionel.debieve@st.com>
Reviewed-by: default avatarChristophe KERELLO <christophe.kerello@st.com>
Change-Id: I03144b133bd51a845a4794f0f6bbd9402fc04936
      495885bc
    • Christophe Kerello's avatar
      drivers: stm32_fmc2_nand: move to new bindings · 0c3e8acb
      Christophe Kerello authored 
      

FMC node bindings are modified to add EBI controller node.
FMC driver and associated device tree files are modified
to support these new bindings.

Change-Id: I4bf201e96a1aca20957e0dac3a3b87caadd05bdc
Signed-off-by: default avatarChristophe Kerello <christophe.kerello@st.com>
Signed-off-by: default avatarLionel Debieve <lionel.debieve@st.com>
      0c3e8acb
  15. 10 Oct, 2020 1 commit
    • johpow01's avatar
      Fix casting bug in gicv2_main.c · 20d38497
      johpow01 authored 
      

In the function gicv2_set_spi_routing, the signed value proc_num is cast
to unsigned int before being compared to other unsigned values in two
assert calls.  The value proc_num can be a negative value, and once the
negative value is cast to unsigned it becomes a very large number which
will trigger the assert.  This patch changes the assert cast so that the
unsigned values are cast to signed instead, keeping the same functionality
but allowing proc_num to be negative.

This bug can be seen when running the SDEI RM_ANY routing mode test in
TFTF on the Juno platform.

This patch also makes the usage of the proc_num variable in other gicv2
functions more clear.
Signed-off-by: default avatarJohn Powell <john.powell@arm.com>
Change-Id: If1b98eebb00bd9b73862e5e995e5e68c168170a6
      20d38497
  17. 09 Oct, 2020 1 commit
    • Jimmy Brisson's avatar
      Don't return error information from console_flush · 831b0e98
      Jimmy Brisson authored 
      

And from crash_console_flush.

We ignore the error information return by console_flush in _every_
place where we call it, and casting the return type to void does not
work around the MISRA violation that this causes. Instead, we collect
the error information from the driver (to avoid changing that API), and
don't return it to the caller.

Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1
Signed-off-by: default avatarJimmy Brisson <jimmy.brisson@arm.com>
      831b0e98
  19. 08 Oct, 2020 1 commit
  21. 04 Oct, 2020 5 commits
  23. 01 Oct, 2020 1 commit
  25. 29 Sep, 2020 1 commit
    • Andre Przywara's avatar
      drivers: arm: gicv3: Allow detecting number of cores · 79d89e3d
      Andre Przywara authored 
      

A GICv3 interrupt controller will be instantiated for a certain number
of cores. This will result in the respective number of GICR frames. The
last frame will have the "Last" bit set in its GICR_TYPER register.

For platforms with a topology unknown at build time (the Arm FPGAs, for
instance), we need to learn the number of used cores at runtime, to size
the GICR region in the devicetree accordingly.

Add a generic function that iterates over all GICR frames until it
encounters one with the "Last" bit set. It returns the number of cores
the GICv3 has been configured for.

Change-Id: I79f033c50dfc1c275aba7122725868811abcc4f8
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      79d89e3d
  27. 28 Sep, 2020 1 commit
  29. 24 Sep, 2020 7 commits
  31. 22 Sep, 2020 1 commit
  33. 14 Sep, 2020 1 commit