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  1. 16 Jul, 2020 1 commit
    • Etienne Carriere's avatar
      stm32mp1: SCMI clock and reset service in SP_MIN · fdaaaeb4
      Etienne Carriere authored 
      

This change implements platform services for stm32mp1 to expose clock
and reset controllers over SCMI clock and reset domain protocols
in sp_min firmware.

Requests execution use a fastcall SMC context using a SiP function ID.
The setup allows the create SCMI channels by assigning a specific
SiP SMC function ID for each channel/agent identifier defined. In this
change, stm32mp1 exposes a single channel and hence expects single
agent at a time.

The input payload in copied in secure memory before the message
in passed through the SCMI server drivers. BL32/sp_min is invoked
for a single SCMI message processing and always returns with a
synchronous response message passed back to the caller agent.

This change fixes and updates STM32_COMMON_SIP_NUM_CALLS that was
previously wrongly set 4 whereas only 1 SiP SMC function ID was to
be counted. STM32_COMMON_SIP_NUM_CALLS is now set to 3 since the
2 added SiP SMC function IDs for SCMI services.

Change-Id: Icb428775856b9aec00538172aea4cf11e609b033
Signed-off-by: default avatarEtienne Carriere <etienne.carriere@st.com>
      fdaaaeb4
  3. 13 Jul, 2020 1 commit
  5. 10 Jul, 2020 8 commits
  7. 09 Jul, 2020 3 commits
  9. 08 Jul, 2020 6 commits
  11. 06 Jul, 2020 1 commit
    • Abdellatif El Khlifi's avatar
      corstone700: splitting the platform support into FVP and FPGA · ef93cfa3
      Abdellatif El Khlifi authored 
      

This patch performs the following:

- Creating two corstone700 platforms under corstone700 board:

  fvp and fpga

- Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform
- The platform can be specified using the TARGET_PLATFORM Makefile variable
(possible values are: fvp or fpga)
- Allowing to use u-boot by:
  - Enabling NEED_BL33 option
  - Fixing non-secure image base: For no preloaded bl33 we want to
    have the NS base set on shared ram. Setup a memory map region
    for NS in shared map and set the bl33 address in the area.
- Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected
platform
- Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY

Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163
Signed-off-by: default avatarRui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: default avatarAbdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
      ef93cfa3
  13. 29 Jun, 2020 2 commits
  15. 27 Jun, 2020 1 commit
  17. 26 Jun, 2020 2 commits
    • Andre Przywara's avatar
      arm_fpga: Fix MPIDR topology checks · 53baf7f0
      Andre Przywara authored 
      

The plat_core_pos_by_mpidr() implementation for the Arm FPGA port has
some issues, which leads to problems when matching GICv3 redistributors
with cores:
- The power domain tree was not taking multithreading into account, so
  we ended up with the wrong mapping between MPIDRs and core IDs.
- Before even considering an MPIDR, we try to make sure Aff2 is 0.
  Unfortunately this is the cluster ID when the MT bit is set.
- We mask off the MT bit in MPIDR, before basing decisions on it.
- When detecting the MT bit, we are properly calculating the thread ID,
  but don't account for the shift in the core and cluster ID checks.

Those problems lead to early rejections of MPIDRs values, in particular
when called from the GIC code. As a result, CPU_ON for secondary cores
was failing for most of the cores.

Fix this by properly handling the MT bit in plat_core_pos_by_mpidr(),
also pulling in FPGA_MAX_PE_PER_CPU when populating the power domain
tree.

Change-Id: I71b2255fc0d27bfe5806511df479ab38e4e33fc4
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      53baf7f0
    • Manish V Badarkhe's avatar
      plat/arm: Use only fw_config between bl2 and bl31 · 7fb9bcd8
      Manish V Badarkhe authored 
      

Passed the address of fw_config instead of soc_fw_config
as arg1 to BL31 from BL2 for ARM fvp platform.

BL31 then retrieve load-address of other device trees
from fw_config device tree.
Signed-off-by: default avatarLouis Mayencourt <louis.mayencourt@arm.com>
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ib7e9581cd765d76111dcc3b7e0dafc12503c83c1
      7fb9bcd8
  19. 25 Jun, 2020 2 commits
    • Manish V Badarkhe's avatar
      plat/arm: Increase size of firmware configuration area · ce4ca1a8
      Manish V Badarkhe authored 
      

Increased the size of firmware configuration area to accommodate
all configs.

Updated maximum size of following bootloaders due to increase
in firmware configs size and addition of the code in the BL2.

1. Increased maximum size of BL2 for Juno platform in no
   optimisation case.
2. Reduced maximum size of BL31 for fvp and Juno platform.
3. Reduced maximum size of BL32 for Juno platform.

Change-Id: Ifba0564df0d1fe86175bed9fae87fdcf013b1831
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
      ce4ca1a8
    • Manish V Badarkhe's avatar
      plat/arm: Load and populate fw_config and tb_fw_config · 82869675
      Manish V Badarkhe authored 
      

Modified the code to do below changes:

1. Load tb_fw_config along with fw_config by BL1.
2. Populate fw_config device tree information in the
   BL1 to load tb_fw_config.
3. In BL2, populate fw_config information to retrieve
   the address of tb_fw_config and then tb_fw_config
   gets populated using retrieved address.
4. Avoid processing of configuration file in case of error
   value returned from "fw_config_load" function.
5. Updated entrypoint information for BL2 image so
   that it's arg0 should point to fw_config address.
Signed-off-by: default avatarManish V Badarkhe <Manish.Badarkhe@arm.com>
Signed-off-by: default avatarLouis Mayencourt <louis.mayencourt@arm.com>
Change-Id: Ife6f7b673a074e7f544ee3d1bda7645fd5b2886c
      82869675
  21. 24 Jun, 2020 6 commits
  23. 23 Jun, 2020 7 commits