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    • Varun Wadekar's avatar
      Tegra: bpmp_ipc: IPC driver to communicate with BPMP firmware · 26e2b93a
      Varun Wadekar authored
      
      
      This patch adds the driver to communicate with the BPMP firmware on Tegra
      SoCs, starting Tegra186. BPMP firmware is responsible for clock enable/
      disable requests, module resets among other things.
      
      MRQ is short for Message ReQuest. This is the general purpose, multi channel
      messaging protocol that is widely used to communicate with BPMP. This is further
      divided into a common high level protocol and a peer-specific low level protocol.
      The higher level protocol specifies the peer identification, channel definition
      and allocation, message structure, message semantics and message dispatch process
      whereas the lower level protocol defines actual message transfer implementation
      details. Currently, BPMP supports two lower level protocols - Token Mail Operations
      (TMO), IVC Mail Operations (IMO).
      
      This driver implements the IMO protocol. IMO is implemented using the IVC (Inter-VM
      Communication) protocol which is a lockless, shared memory messaging queue management
      protocol.
      
      The IVC peer is expected to perform the following as part of establishing a connection
      with BPMP.
      
      1. Initialize the channels with tegra_ivc_init() or its equivalent.
      2. Reset the channel with tegra_ivc_channel_reset. The peer should also ensure that
         BPMP is notified via the doorbell.
      3. Poll until the channel connection is established [tegra_ivc_channel_notified() return
         0]. Interrupt BPMP with doorbell each time after tegra_ivc_channel_notified() return
         non zero.
      
      The IPC driver currently supports reseting the GPCDMAand XUSB_PADCTL hardware blocks. In
      future, more hardware blocks would be supported.
      
      Change-Id: I52a4bd3a853de6c4fa410904b6614ff1c63df364
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      26e2b93a