# # Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # PROGRAMMABLE_RESET_ADDRESS := 0 COLD_BOOT_SINGLE_CPU := 1 ARM_CCI_PRODUCT_ID := 500 TRUSTED_BOARD_BOOT := 1 RESET_TO_BL31 := 1 GENERATE_COT := 1 BL2_AT_EL3 := 1 ENABLE_SVE_FOR_NS := 0 MULTI_CONSOLE_API := 1 CRASH_REPORTING := 1 HANDLE_EA_EL3_FIRST := 1 $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) ifeq (${SPD},none) SPD_NONE:=1 $(eval $(call add_define,SPD_NONE)) endif # LSI setting common define RCAR_H3:=0 RCAR_M3:=1 RCAR_M3N:=2 RCAR_E3:=3 RCAR_H3N:=4 RCAR_D3:=5 RCAR_V3M:=6 RCAR_AUTO:=99 $(eval $(call add_define,RCAR_H3)) $(eval $(call add_define,RCAR_M3)) $(eval $(call add_define,RCAR_M3N)) $(eval $(call add_define,RCAR_E3)) $(eval $(call add_define,RCAR_H3N)) $(eval $(call add_define,RCAR_D3)) $(eval $(call add_define,RCAR_V3M)) $(eval $(call add_define,RCAR_AUTO)) RCAR_CUT_10:=0 RCAR_CUT_11:=1 RCAR_CUT_13:=3 RCAR_CUT_20:=10 RCAR_CUT_30:=20 $(eval $(call add_define,RCAR_CUT_10)) $(eval $(call add_define,RCAR_CUT_11)) $(eval $(call add_define,RCAR_CUT_13)) $(eval $(call add_define,RCAR_CUT_20)) $(eval $(call add_define,RCAR_CUT_30)) # Enable workarounds for selected Cortex-A53 erratas. ERRATA_A53_835769 := 1 ERRATA_A53_843419 := 1 ERRATA_A53_855873 := 1 # Enable workarounds for selected Cortex-A57 erratas. ERRATA_A57_859972 := 1 ERRATA_A57_813419 := 1 PLAT_INCLUDES := -Iplat/renesas/common/include/registers \ -Iplat/renesas/common/include \ -Iplat/renesas/common RCAR_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ drivers/arm/gic/v2/gicv2_main.c \ drivers/arm/gic/v2/gicv2_helpers.c \ plat/common/plat_gicv2.c BL2_SOURCES += ${RCAR_GIC_SOURCES} \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ ${LIBFDT_SRCS} \ common/desc_image_load.c \ drivers/renesas/common/common.c \ drivers/io/io_storage.c BL31_SOURCES += ${RCAR_GIC_SOURCES} \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ plat/common/plat_psci_common.c \ drivers/renesas/common/common.c \ drivers/arm/cci/cci.c