/* * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __TEGRA_DEF_H__ #define __TEGRA_DEF_H__ #include /******************************************************************************* * These values are used by the PSCI implementation during the `CPU_SUSPEND` * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' * parameter. ******************************************************************************/ #define PSTATE_ID_CORE_IDLE 6 #define PSTATE_ID_CORE_POWERDN 7 #define PSTATE_ID_SOC_POWERDN 2 /******************************************************************************* * Platform power states (used by PSCI framework) * * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID ******************************************************************************/ #define PLAT_MAX_RET_STATE 1 #define PLAT_MAX_OFF_STATE 8 /******************************************************************************* * Implementation defined ACTLR_EL3 bit definitions ******************************************************************************/ #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) #define ACTLR_EL3_L2CTLR_BIT (1 << 4) #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) #define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ ACTLR_EL3_L2ECTLR_BIT | \ ACTLR_EL3_L2CTLR_BIT | \ ACTLR_EL3_CPUECTLR_BIT | \ ACTLR_EL3_CPUACTLR_BIT) /******************************************************************************* * Secure IRQ definitions ******************************************************************************/ #define TEGRA186_TOP_WDT_IRQ 49 #define TEGRA186_AON_WDT_IRQ 50 #define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */ /******************************************************************************* * Tegra Miscellanous register constants ******************************************************************************/ #define TEGRA_MISC_BASE 0x00100000 #define HARDWARE_REVISION_OFFSET 0x4 #define HARDWARE_MINOR_REVISION_MASK 0xf0000 #define HARDWARE_MINOR_REVISION_SHIFT 0x10 #define HARDWARE_REVISION_A01 1 #define MISCREG_PFCFG 0x200C /******************************************************************************* * Tegra Memory Controller constants ******************************************************************************/ #define TEGRA_MC_STREAMID_BASE 0x02C00000 #define TEGRA_MC_BASE 0x02C10000 /******************************************************************************* * Tegra UART Controller constants ******************************************************************************/ #define TEGRA_UARTA_BASE 0x03100000 #define TEGRA_UARTB_BASE 0x03110000 #define TEGRA_UARTC_BASE 0x0C280000 #define TEGRA_UARTD_BASE 0x03130000 #define TEGRA_UARTE_BASE 0x03140000 #define TEGRA_UARTF_BASE 0x03150000 #define TEGRA_UARTG_BASE 0x0C290000 /******************************************************************************* * GICv2 & interrupt handling related constants ******************************************************************************/ #define TEGRA_GICD_BASE 0x03881000 #define TEGRA_GICC_BASE 0x03882000 /******************************************************************************* * Security Engine related constants ******************************************************************************/ #define TEGRA_SE0_BASE 0x03AC0000 #define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C #define TEGRA_PKA1_BASE 0x03AD0000 #define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 #define TEGRA_RNG1_BASE 0x03AE0000 #define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 /******************************************************************************* * Tegra Clock and Reset Controller constants ******************************************************************************/ #define TEGRA_CAR_RESET_BASE 0x05000000 /******************************************************************************* * Tegra micro-seconds timer constants ******************************************************************************/ #define TEGRA_TMRUS_BASE 0x0C2E0000 /******************************************************************************* * Tegra Power Mgmt Controller constants ******************************************************************************/ #define TEGRA_PMC_BASE 0x0C360000 /******************************************************************************* * Tegra scratch registers constants ******************************************************************************/ #define TEGRA_SCRATCH_BASE 0x0C390000 #define SECURE_SCRATCH_RSV6 0x680 #define SECURE_SCRATCH_RSV11_LO 0x6A8 #define SECURE_SCRATCH_RSV11_HI 0x6AC /******************************************************************************* * Tegra Memory Mapped Control Register Access Bus constants ******************************************************************************/ #define TEGRA_MMCRAB_BASE 0x0E000000 /******************************************************************************* * Tegra SMMU Controller constants ******************************************************************************/ #define TEGRA_SMMU_BASE 0x12000000 /******************************************************************************* * Tegra TZRAM constants ******************************************************************************/ #define TEGRA_TZRAM_BASE 0x30000000 #define TEGRA_TZRAM_SIZE 0x50000 #endif /* __TEGRA_DEF_H__ */