/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout * of trusted SRAM ******************************************************************************/ extern unsigned long __RO_START__; extern unsigned long __COHERENT_RAM_END__; /******************************************************************************* * Lock to control access to the console ******************************************************************************/ spinlock_t console_lock; /******************************************************************************* * Per cpu data structure to populate parameters for an SMC in C code and use * a pointer to this structure in assembler code to populate x0-x7 ******************************************************************************/ static tsp_args_t tsp_smc_args[PLATFORM_CORE_COUNT]; /******************************************************************************* * Per cpu data structure to keep track of TSP activity ******************************************************************************/ work_statistics_t tsp_stats[PLATFORM_CORE_COUNT]; /******************************************************************************* * The BL32 memory footprint starts with an RO sections and ends * with a section for coherent RAM. Use it to find the memory size ******************************************************************************/ #define BL32_TOTAL_BASE (unsigned long)(&__RO_START__) #define BL32_TOTAL_LIMIT (unsigned long)(&__COHERENT_RAM_END__) static tsp_args_t *set_smc_args(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, uint64_t arg6, uint64_t arg7) { uint64_t mpidr = read_mpidr(); uint32_t linear_id; tsp_args_t *pcpu_smc_args; /* * Return to Secure Monitor by raising an SMC. The results of the * service are passed as an arguments to the SMC */ linear_id = platform_get_core_pos(mpidr); pcpu_smc_args = &tsp_smc_args[linear_id]; write_sp_arg(pcpu_smc_args, TSP_ARG0, arg0); write_sp_arg(pcpu_smc_args, TSP_ARG1, arg1); write_sp_arg(pcpu_smc_args, TSP_ARG2, arg2); write_sp_arg(pcpu_smc_args, TSP_ARG3, arg3); write_sp_arg(pcpu_smc_args, TSP_ARG4, arg4); write_sp_arg(pcpu_smc_args, TSP_ARG5, arg5); write_sp_arg(pcpu_smc_args, TSP_ARG6, arg6); write_sp_arg(pcpu_smc_args, TSP_ARG7, arg7); return pcpu_smc_args; } /******************************************************************************* * TSP main entry point where it gets the opportunity to initialize its secure * state/applications. Once the state is initialized, it must return to the * SPD with a pointer to the 'tsp_vector_table' jump table. ******************************************************************************/ uint64_t tsp_main(void) { uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); /* Initialize the platform */ bl32_platform_setup(); /* Initialize secure/applications state here */ tsp_generic_timer_start(); /* Update this cpu's statistics */ tsp_stats[linear_id].smc_count++; tsp_stats[linear_id].eret_count++; tsp_stats[linear_id].cpu_on_count++; spin_lock(&console_lock); printf("TSP %s\n\r", build_message); INFO("Total memory base : 0x%x\n", (unsigned long)BL32_TOTAL_BASE); INFO("Total memory size : 0x%x bytes\n", (unsigned long)(BL32_TOTAL_LIMIT - BL32_TOTAL_BASE)); INFO("cpu 0x%x: %d smcs, %d erets %d cpu on requests\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, tsp_stats[linear_id].cpu_on_count); spin_unlock(&console_lock); return (uint64_t) &tsp_vector_table; } /******************************************************************************* * This function performs any remaining book keeping in the test secure payload * after this cpu's architectural state has been setup in response to an earlier * psci cpu_on request. ******************************************************************************/ tsp_args_t *tsp_cpu_on_main(void) { uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); /* Initialize secure/applications state here */ tsp_generic_timer_start(); /* Update this cpu's statistics */ tsp_stats[linear_id].smc_count++; tsp_stats[linear_id].eret_count++; tsp_stats[linear_id].cpu_on_count++; spin_lock(&console_lock); printf("SP: cpu 0x%x turned on\n\r", mpidr); INFO("cpu 0x%x: %d smcs, %d erets %d cpu on requests\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, tsp_stats[linear_id].cpu_on_count); spin_unlock(&console_lock); /* Indicate to the SPD that we have completed turned ourselves on */ return set_smc_args(TSP_ON_DONE, 0, 0, 0, 0, 0, 0, 0); } /******************************************************************************* * This function performs any remaining book keeping in the test secure payload * before this cpu is turned off in response to a psci cpu_off request. ******************************************************************************/ tsp_args_t *tsp_cpu_off_main(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, uint64_t arg6, uint64_t arg7) { uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); /* * This cpu is being turned off, so disable the timer to prevent the * secure timer interrupt from interfering with power down. A pending * interrupt will be lost but we do not care as we are turning off. */ tsp_generic_timer_stop(); /* Update this cpu's statistics */ tsp_stats[linear_id].smc_count++; tsp_stats[linear_id].eret_count++; tsp_stats[linear_id].cpu_off_count++; spin_lock(&console_lock); printf("SP: cpu 0x%x off request\n\r", mpidr); INFO("cpu 0x%x: %d smcs, %d erets %d cpu off requests\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, tsp_stats[linear_id].cpu_off_count); spin_unlock(&console_lock); /* Indicate to the SPD that we have completed this request */ return set_smc_args(TSP_OFF_DONE, 0, 0, 0, 0, 0, 0, 0); } /******************************************************************************* * This function performs any book keeping in the test secure payload before * this cpu's architectural state is saved in response to an earlier psci * cpu_suspend request. ******************************************************************************/ tsp_args_t *tsp_cpu_suspend_main(uint64_t power_state, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, uint64_t arg6, uint64_t arg7) { uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); /* * Save the time context and disable it to prevent the secure timer * interrupt from interfering with wakeup from the suspend state. */ tsp_generic_timer_save(); tsp_generic_timer_stop(); /* Update this cpu's statistics */ tsp_stats[linear_id].smc_count++; tsp_stats[linear_id].eret_count++; tsp_stats[linear_id].cpu_suspend_count++; spin_lock(&console_lock); printf("SP: cpu 0x%x suspend request. power state: 0x%x\n\r", mpidr, power_state); INFO("cpu 0x%x: %d smcs, %d erets %d cpu suspend requests\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, tsp_stats[linear_id].cpu_suspend_count); spin_unlock(&console_lock); /* Indicate to the SPD that we have completed this request */ return set_smc_args(TSP_SUSPEND_DONE, 0, 0, 0, 0, 0, 0, 0); } /******************************************************************************* * This function performs any book keeping in the test secure payload after this * cpu's architectural state has been restored after wakeup from an earlier psci * cpu_suspend request. ******************************************************************************/ tsp_args_t *tsp_cpu_resume_main(uint64_t suspend_level, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, uint64_t arg6, uint64_t arg7) { uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); /* Restore the generic timer context */ tsp_generic_timer_restore(); /* Update this cpu's statistics */ tsp_stats[linear_id].smc_count++; tsp_stats[linear_id].eret_count++; tsp_stats[linear_id].cpu_resume_count++; spin_lock(&console_lock); printf("SP: cpu 0x%x resumed. suspend level %d \n\r", mpidr, suspend_level); INFO("cpu 0x%x: %d smcs, %d erets %d cpu suspend requests\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, tsp_stats[linear_id].cpu_suspend_count); spin_unlock(&console_lock); /* Indicate to the SPD that we have completed this request */ return set_smc_args(TSP_RESUME_DONE, 0, 0, 0, 0, 0, 0, 0); } /******************************************************************************* * TSP fast smc handler. The secure monitor jumps to this function by * doing the ERET after populating X0-X7 registers. The arguments are received * in the function arguments in order. Once the service is rendered, this * function returns to Secure Monitor by raising SMC. ******************************************************************************/ tsp_args_t *tsp_smc_handler(uint64_t func, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, uint64_t arg6, uint64_t arg7) { uint64_t results[2]; uint64_t service_args[2]; uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); const char *smc_type; /* Update this cpu's statistics */ tsp_stats[linear_id].smc_count++; tsp_stats[linear_id].eret_count++; smc_type = ((func >> 31) & 1) == 1 ? "fast" : "standard"; printf("SP: cpu 0x%x received %s smc 0x%x\n", read_mpidr(), smc_type, func); INFO("cpu 0x%x: %d smcs, %d erets\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count); /* Render secure services and obtain results here */ results[0] = arg1; results[1] = arg2; /* * Request a service back from dispatcher/secure monitor. This call * return and thereafter resume exectuion */ tsp_get_magic(service_args); /* Determine the function to perform based on the function ID */ switch (TSP_BARE_FID(func)) { case TSP_ADD: results[0] += service_args[0]; results[1] += service_args[1]; break; case TSP_SUB: results[0] -= service_args[0]; results[1] -= service_args[1]; break; case TSP_MUL: results[0] *= service_args[0]; results[1] *= service_args[1]; break; case TSP_DIV: results[0] /= service_args[0] ? service_args[0] : 1; results[1] /= service_args[1] ? service_args[1] : 1; break; default: break; } return set_smc_args(func, 0, results[0], results[1], 0, 0, 0, 0); }