/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include "../fvp_def.h" .section .rodata.gic_reg_name, "aS" gic_regs: .asciz "gic_iar", "gic_ctlr", "" /* Currently we have only 2 GIC registers to report */ #define GIC_REG_SIZE (2 * 8) /* --------------------------------------------- * The below macro prints out relevant GIC * registers whenever an unhandled exception is * taken in BL31. * --------------------------------------------- */ .macro plat_print_gic_regs mov x0, #CONFIG_GICC_ADDR bl platform_get_cfgvar /* gic base address is now in x0 */ ldr w1, [x0, #GICC_IAR] ldr w2, [x0, #GICD_CTLR] sub sp, sp, #GIC_REG_SIZE stp x1, x2, [sp] /* we store the gic registers as 64 bit */ adr x0, gic_regs mov x1, sp bl print_string_value add sp, sp, #GIC_REG_SIZE .endm