Merge pull request #154 from apritzel/larger_spl

fel: Allow larger SPL payload

fel.c

@@ -715,13 +715,10 @@ void aw_restore_and_enable_mmu(feldev_handle *dev,
 	free(tt);
 }
 
-/*
- * Maximum size of SPL, at the same time this is the start offset
- * of the main U-Boot image within u-boot-sunxi-with-spl.bin
- */
-#define SPL_LEN_LIMIT 0x8000
+/* Minimum offset of the main U-Boot image within u-boot-sunxi-with-spl.bin. */
+#define SPL_MIN_OFFSET 0x8000
 
-void aw_fel_write_and_execute_spl(feldev_handle *dev, uint8_t *buf, size_t len)
+uint32_t aw_fel_write_and_execute_spl(feldev_handle *dev, uint8_t *buf, size_t len)
 {
 	soc_info_t *soc_info = dev->soc_info;
 	sram_swap_buffers *swap_buffers;
@@ -729,7 +726,7 @@ void aw_fel_write_and_execute_spl(feldev_handle *dev, uint8_t *buf, size_t len)
 	size_t i, thunk_size;
 	uint32_t *thunk_buf;
 	uint32_t sp, sp_irq;
-	uint32_t spl_checksum, spl_len, spl_len_limit = SPL_LEN_LIMIT;
+	uint32_t spl_checksum, spl_len, spl_len_limit;
 	uint32_t *buf32 = (uint32_t *)buf;
 	uint32_t cur_addr = soc_info->spl_addr;
 	uint32_t *tt = NULL;
@@ -782,6 +779,8 @@ void aw_fel_write_and_execute_spl(feldev_handle *dev, uint8_t *buf, size_t len)
 		tt = aw_generate_mmu_translation_table();
 	}
 
+	spl_len_limit = soc_info->sram_size;
+
 	swap_buffers = soc_info->swap_buffers;
 	for (i = 0; swap_buffers[i].size; i++) {
 		if ((swap_buffers[i].buf2 >= soc_info->spl_addr) &&
@@ -808,8 +807,8 @@ void aw_fel_write_and_execute_spl(feldev_handle *dev, uint8_t *buf, size_t len)
 	}
 
 	/* Clarify the SPL size limitations, and bail out if they are not met */
-	if (soc_info->thunk_addr < spl_len_limit)
-		spl_len_limit = soc_info->thunk_addr;
+	if (soc_info->thunk_addr - soc_info->spl_addr < spl_len_limit)
+		spl_len_limit = soc_info->thunk_addr - soc_info->spl_addr;
 
 	if (spl_len > spl_len_limit)
 		pr_fatal("SPL: too large (need %u, have %u)\n",
@@ -855,6 +854,8 @@ void aw_fel_write_and_execute_spl(feldev_handle *dev, uint8_t *buf, size_t len)
 	/* re-enable the MMU if it was enabled by BROM */
 	if (tt != NULL)
 		aw_restore_and_enable_mmu(dev, soc_info, tt);
+
+	return spl_len;
 }
 
 /*
@@ -870,15 +871,6 @@ void aw_fel_write_uboot_image(feldev_handle *dev, uint8_t *buf, size_t len)
 
 	image_header_t hdr = *(image_header_t *)buf;
 
-	uint32_t hcrc = be32toh(hdr.ih_hcrc);
-
-	/* The CRC is calculated on the whole header but the CRC itself */
-	hdr.ih_hcrc = 0;
-	uint32_t computed_hcrc = crc32(0, (const uint8_t *) &hdr, HEADER_SIZE);
-	if (hcrc != computed_hcrc)
-		pr_fatal("U-Boot header CRC mismatch: expected %x, got %x\n",
-			 hcrc, computed_hcrc);
-
 	/* Check for a valid mkimage header */
 	int image_type = get_image_type(buf, len);
 	if (image_type <= IH_TYPE_INVALID) {
@@ -899,6 +891,14 @@ void aw_fel_write_uboot_image(feldev_handle *dev, uint8_t *buf, size_t len)
 		pr_fatal("U-Boot image type mismatch: "
 			 "expected IH_TYPE_FIRMWARE, got %02X\n", image_type);
 
+	/* The CRC is calculated on the whole header but the CRC itself */
+	uint32_t hcrc = be32toh(hdr.ih_hcrc);
+	hdr.ih_hcrc = 0;
+	uint32_t computed_hcrc = crc32(0, (const uint8_t *) &hdr, HEADER_SIZE);
+	if (hcrc != computed_hcrc)
+		pr_fatal("U-Boot header CRC mismatch: expected %x, got %x\n",
+			 hcrc, computed_hcrc);
+
 	uint32_t data_size = be32toh(hdr.ih_size); /* Image Data Size */
 	uint32_t load_addr = be32toh(hdr.ih_load); /* Data Load Address */
 	if (data_size > len - HEADER_SIZE)
@@ -928,14 +928,20 @@ void aw_fel_write_uboot_image(feldev_handle *dev, uint8_t *buf, size_t len)
  */
 void aw_fel_process_spl_and_uboot(feldev_handle *dev, const char *filename)
 {
-	/* load file into memory buffer */
 	size_t size;
+	uint32_t offset;
+	/* load file into memory buffer */
 	uint8_t *buf = load_file(filename, &size);
+
 	/* write and execute the SPL from the buffer */
-	aw_fel_write_and_execute_spl(dev, buf, size);
+	offset = aw_fel_write_and_execute_spl(dev, buf, size);
 	/* check for optional main U-Boot binary (and transfer it, if applicable) */
-	if (size > SPL_LEN_LIMIT)
-		aw_fel_write_uboot_image(dev, buf + SPL_LEN_LIMIT, size - SPL_LEN_LIMIT);
+	if (size > offset) {
+		/* U-Boot pads to at least 32KB */
+		if (offset < SPL_MIN_OFFSET)
+			offset = SPL_MIN_OFFSET;
+		aw_fel_write_uboot_image(dev, buf + offset, size - offset);
+	}
 	free(buf);
 }
 

soc_info.c

@@ -60,16 +60,18 @@ sram_swap_buffers a31_sram_swap_buffers[] = {
 /*
  * A64 has 32KiB of SRAM A at 0x10000 and a large SRAM C at 0x18000. SRAM A
  * and SRAM C reside in the address space back-to-back without any gaps, thus
- * representing a singe large contiguous area. Everything is the same as on
- * A10/A13/A20, but just shifted by 0x10000.
+ * representing a singe large contiguous area. The BROM FEL code memory areas
+ * are the same as on A10/A13/A20, but just shifted by 0x10000.
+ * We put the backup buffers towards the end of SRAM C, in a location that
+ * is also available on the H5.
  */
 sram_swap_buffers a64_sram_swap_buffers[] = {
 	/* 0x11C00-0x11FFF (IRQ stack) */
-	{ .buf1 = 0x11C00, .buf2 = 0x1A400, .size = 0x0400 },
+	{ .buf1 = 0x11C00, .buf2 = 0x31400, .size = 0x0400 },
 	/* 0x15C00-0x16FFF (Stack) */
-	{ .buf1 = 0x15C00, .buf2 = 0x1A800, .size = 0x1400 },
+	{ .buf1 = 0x15C00, .buf2 = 0x31800, .size = 0x1400 },
 	/* 0x17C00-0x17FFF (Something important) */
-	{ .buf1 = 0x17C00, .buf2 = 0x1BC00, .size = 0x0400 },
+	{ .buf1 = 0x17C00, .buf2 = 0x32c00, .size = 0x0400 },
 	{ .size = 0 }  /* End of the table */
 };
 
@@ -102,11 +104,11 @@ sram_swap_buffers a80_sram_swap_buffers[] = {
  */
 sram_swap_buffers h6_sram_swap_buffers[] = {
 	/* 0x21C00-0x21FFF (IRQ stack) */
-	{ .buf1 = 0x21C00, .buf2 = 0x2A400, .size = 0x0400 },
+	{ .buf1 = 0x21C00, .buf2 = 0x42400, .size = 0x0400 },
 	/* 0x25C00-0x26FFF (Stack) */
-	{ .buf1 = 0x25C00, .buf2 = 0x2A800, .size = 0x1400 },
+	{ .buf1 = 0x25C00, .buf2 = 0x42800, .size = 0x1400 },
 	/* 0x27C00-0x27FFF (Something important) */
-	{ .buf1 = 0x27C00, .buf2 = 0x2BC00, .size = 0x0400 },
+	{ .buf1 = 0x27C00, .buf2 = 0x43c00, .size = 0x0400 },
 	{ .size = 0 }  /* End of the table */
 };
 
@@ -127,7 +129,7 @@ sram_swap_buffers v831_sram_swap_buffers[] = {
 
 /* H616 situation is the same as V831 one, except it has 32 KiB of SRAM A1. */
 sram_swap_buffers h616_sram_swap_buffers[] = {
-	{ .buf1 = 0x21000, .buf2 = 0x28000, .size = 0x1000 },
+	{ .buf1 = 0x21000, .buf2 = 0x52a00, .size = 0x1000 },
 	{ .size = 0 }  /* End of the table */
 };
 
@@ -158,6 +160,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x1000,
 		.thunk_addr   = 0xA200, .thunk_size = 0x200,
 		.swap_buffers = a10_a13_a20_sram_swap_buffers,
+		.sram_size    = 48 * 1024,
 		.needs_l2en   = true,
 		.sid_base     = 0x01C23800,
 		.watchdog     = &wd_a10_compat,
@@ -167,6 +170,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x1000,
 		.thunk_addr   = 0xA200, .thunk_size = 0x200,
 		.swap_buffers = a10_a13_a20_sram_swap_buffers,
+		.sram_size    = 48 * 1024,
 		.needs_l2en   = true,
 		.sid_base     = 0x01C23800,
 		.watchdog     = &wd_a10_compat,
@@ -176,6 +180,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x1000,
 		.thunk_addr   = 0xA200, .thunk_size = 0x200,
 		.swap_buffers = a10_a13_a20_sram_swap_buffers,
+		.sram_size    = 48 * 1024,
 		.sid_base     = 0x01C23800,
 		.watchdog     = &wd_a10_compat,
 	},{
@@ -184,6 +189,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x1000,
 		.thunk_addr   = 0x46E00, .thunk_size = 0x200,
 		.swap_buffers = ar100_abusing_sram_swap_buffers,
+		.sram_size    = 64 * 1024,
 		.sid_base     = 0x01C23800,
 		.watchdog     = &wd_h3_compat,
 	},{
@@ -192,6 +198,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x1000,
 		.thunk_addr   = 0x22E00, .thunk_size = 0x200,
 		.swap_buffers = a31_sram_swap_buffers,
+		.sram_size    = 32 * 1024,
 		.watchdog     = &wd_h3_compat,
 	},{
 		.soc_id       = 0x1667, /* Allwinner A33, R16 */
@@ -199,6 +206,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x1000,
 		.thunk_addr   = 0x46E00, .thunk_size = 0x200,
 		.swap_buffers = ar100_abusing_sram_swap_buffers,
+		.sram_size    = 32 * 1024,
 		.sid_base     = 0x01C23800,
 		.watchdog     = &wd_h3_compat,
 	},{
@@ -206,8 +214,9 @@ soc_info_t soc_info_table[] = {
 		.name         = "A64",
 		.spl_addr     = 0x10000,
 		.scratch_addr = 0x11000,
-		.thunk_addr   = 0x1A200, .thunk_size = 0x200,
+		.thunk_addr   = 0x31200, .thunk_size = 0x200,
 		.swap_buffers = a64_sram_swap_buffers,
+		.sram_size    = 140 * 1024,
 		.sid_base     = 0x01C14000,
 		.sid_offset   = 0x200,
 		.rvbar_reg    = 0x017000A0,
@@ -221,6 +230,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x11000,
 		.thunk_addr   = 0x23400, .thunk_size = 0x200,
 		.swap_buffers = a80_sram_swap_buffers,
+		.sram_size    = 40 * 1024,
 		.sid_base     = 0X01C0E000,
 		.sid_offset   = 0x200,
 		.watchdog     = &wd_a80,
@@ -231,6 +241,7 @@ soc_info_t soc_info_table[] = {
 		.mmu_tt_addr  = 0x44000,
 		.thunk_addr   = 0x46E00, .thunk_size = 0x200,
 		.swap_buffers = ar100_abusing_sram_swap_buffers,
+		.sram_size    = 32 * 1024,
 		.sid_base     = 0x01C14000,
 		.sid_offset   = 0x200,
 		.watchdog     = &wd_h3_compat,
@@ -241,6 +252,7 @@ soc_info_t soc_info_table[] = {
 		.mmu_tt_addr  = 0x8000,
 		.thunk_addr   = 0xA200, .thunk_size = 0x200,
 		.swap_buffers = a10_a13_a20_sram_swap_buffers,
+		.sram_size    = 108 * 1024,
 		.sid_base     = 0x01C14000,
 		.sid_offset   = 0x200,
 		.sid_fix      = true,
@@ -254,6 +266,7 @@ soc_info_t soc_info_table[] = {
 		.mmu_tt_addr  = 0x8000,
 		.thunk_addr   = 0xA200, .thunk_size = 0x200,
 		.swap_buffers = a10_a13_a20_sram_swap_buffers,
+		.sram_size    = 60 * 1024,
 		.sid_base     = 0x01C23800,
 		.watchdog     = &wd_h3_compat,
 	},{
@@ -261,8 +274,9 @@ soc_info_t soc_info_table[] = {
 		.name         = "H5",
 		.spl_addr     = 0x10000,
 		.scratch_addr = 0x11000,
-		.thunk_addr   = 0x1A200, .thunk_size = 0x200,
+		.thunk_addr   = 0x31200, .thunk_size = 0x200,
 		.swap_buffers = a64_sram_swap_buffers,
+		.sram_size    = 140 * 1024,
 		.sid_base     = 0x01C14000,
 		.sid_offset   = 0x200,
 		.rvbar_reg    = 0x017000A0,
@@ -275,6 +289,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x1000,
 		.thunk_addr   = 0xA200, .thunk_size = 0x200,
 		.swap_buffers = a10_a13_a20_sram_swap_buffers,
+		.sram_size    = 48 * 1024,
 		.sid_base     = 0x01C1B000,
 		.sid_offset   = 0x200,
 		.watchdog     = &wd_a10_compat,
@@ -283,8 +298,9 @@ soc_info_t soc_info_table[] = {
 		.name         = "H6",
 		.spl_addr     = 0x20000,
 		.scratch_addr = 0x21000,
-		.thunk_addr   = 0x2A200, .thunk_size = 0x200,
+		.thunk_addr   = 0x42200, .thunk_size = 0x200,
 		.swap_buffers = h6_sram_swap_buffers,
+		.sram_size    = 144 * 1024,
 		.sid_base     = 0x03006000,
 		.sid_offset   = 0x200,
 		.rvbar_reg    = 0x09010040,
@@ -298,6 +314,7 @@ soc_info_t soc_info_table[] = {
 		.scratch_addr = 0x21000,
 		.thunk_addr   = 0x2A200, .thunk_size = 0x200,
 		.swap_buffers = v831_sram_swap_buffers,
+		.sram_size    = 228 * 1024,
 		.sid_base     = 0x03006000,
 		.sid_offset   = 0x200,
 		.watchdog     = &wd_h6_compat,
@@ -306,8 +323,9 @@ soc_info_t soc_info_table[] = {
 		.name         = "H616",
 		.spl_addr     = 0x20000,
 		.scratch_addr = 0x21000,
-		.thunk_addr   = 0x2A200, .thunk_size = 0x200,
+		.thunk_addr   = 0x53a00, .thunk_size = 0x200,
 		.swap_buffers = h616_sram_swap_buffers,
+		.sram_size    = 207 * 1024,
 		.sid_base     = 0x03006000,
 		.sid_offset   = 0x200,
 		.rvbar_reg    = 0x09010040,

soc_info.h

@@ -115,6 +115,7 @@ typedef struct {
 	bool               sid_fix;      /* Use SID workaround (read via register) */
 	/* Use SMC workaround (enter secure mode) if can't read from this address */
 	uint32_t           needs_smc_workaround_if_zero_word_at_addr;
+	uint32_t           sram_size;	/* Usable contiguous SRAM at spl_addr */
 	sram_swap_buffers *swap_buffers;
 } soc_info_t;