fel: Factor out SoC information (and SRAM buffers) retrieval

While at it, modify the former "sram_info" identifiers
to carry a broader "soc_info" meaning.
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>

Makefile

@@ -121,7 +121,10 @@ endif
 
 HOST_CFLAGS = $(DEFAULT_CFLAGS) $(CFLAGS)
 
-sunxi-fel: fel.c fel-to-spl-thunk.h progress.c progress.h
+PROGRESS = progress.c progress.h
+SOC_INFO = soc_info.c soc_info.h
+
+sunxi-fel: fel.c fel-to-spl-thunk.h $(PROGRESS) $(SOC_INFO)
 	$(CC) $(HOST_CFLAGS) $(LIBUSB_CFLAGS) $(LDFLAGS) -o $@ $(filter %.c,$^) $(LIBS) $(LIBUSB_LIBS)
 
 sunxi-nand-part: nand-part-main.c nand-part.c nand-part-a10.h nand-part-a20.h

soc_info.c

+/*
+ * Copyright (C) 2012  Henrik Nordstrom <henrik@henriknordstrom.net>
+ * Copyright (C) 2015  Siarhei Siamashka <siarhei.siamashka@gmail.com>
+ * Copyright (C) 2016  Bernhard Nortmann <bernhard.nortmann@web.de>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**********************************************************************
+ * SoC information and retrieval of soc_sram_info
+ **********************************************************************/
+#include "soc_info.h"
+
+#include <stdio.h>
+#include <unistd.h>
+
+/*
+ * The FEL code from BROM in A10/A13/A20 sets up two stacks for itself. One
+ * at 0x2000 (and growing down) for the IRQ handler. And another one at 0x7000
+ * (and also growing down) for the regular code. In order to use the whole
+ * 32 KiB in the A1/A2 sections of SRAM, we need to temporarily move these
+ * stacks elsewhere. And the addresses 0x7D00-0x7FFF contain something
+ * important too (overwriting them kills FEL). On A10/A13/A20 we can use
+ * the SRAM sections A3/A4 (0x8000-0xBFFF) for this purpose.
+ */
+sram_swap_buffers a10_a13_a20_sram_swap_buffers[] = {
+	/* 0x1C00-0x1FFF (IRQ stack) */
+	{ .buf1 = 0x1C00, .buf2 = 0xA400, .size = 0x0400 },
+	/* 0x5C00-0x6FFF (Stack) */
+	{ .buf1 = 0x5C00, .buf2 = 0xA800, .size = 0x1400 },
+	/* 0x7C00-0x7FFF (Something important) */
+	{ .buf1 = 0x7C00, .buf2 = 0xBC00, .size = 0x0400 },
+	{ .size = 0 }  /* End of the table */
+};
+
+/*
+ * A31 is very similar to A10/A13/A20, except that it has no SRAM at 0x8000.
+ * So we use the SRAM section B at 0x20000-0x2FFFF instead. In the FEL mode,
+ * the MMU translation table is allocated by the BROM at 0x20000. But we can
+ * also safely use it as the backup storage because the MMU is temporarily
+ * disabled during the time of the SPL execution.
+ */
+sram_swap_buffers a31_sram_swap_buffers[] = {
+	{ .buf1 = 0x1800, .buf2 = 0x20000, .size = 0x800 },
+	{ .buf1 = 0x5C00, .buf2 = 0x20800, .size = 0x8000 - 0x5C00 },
+	{ .size = 0 }  /* End of the table */
+};
+
+/*
+ * A64 has 32KiB of SRAM A at 0x10000 and a large SRAM C at 0x18000. SRAM A
+ * and SRAM C reside in the address space back-to-back without any gaps, thus
+ * representing a singe large contiguous area. Everything is the same as on
+ * A10/A13/A20, but just shifted by 0x10000.
+ */
+sram_swap_buffers a64_sram_swap_buffers[] = {
+	/* 0x11C00-0x11FFF (IRQ stack) */
+	{ .buf1 = 0x11C00, .buf2 = 0x1A400, .size = 0x0400 },
+	/* 0x15C00-0x16FFF (Stack) */
+	{ .buf1 = 0x15C00, .buf2 = 0x1A800, .size = 0x1400 },
+	/* 0x17C00-0x17FFF (Something important) */
+	{ .buf1 = 0x17C00, .buf2 = 0x1BC00, .size = 0x0400 },
+	{ .size = 0 }  /* End of the table */
+};
+
+/*
+ * Use the SRAM section at 0x44000 as the backup storage. This is the memory,
+ * which is normally shared with the OpenRISC core (should we do an extra check
+ * to ensure that this core is powered off and can't interfere?).
+ */
+sram_swap_buffers ar100_abusing_sram_swap_buffers[] = {
+	{ .buf1 = 0x1800, .buf2 = 0x44000, .size = 0x800 },
+	{ .buf1 = 0x5C00, .buf2 = 0x44800, .size = 0x8000 - 0x5C00 },
+	{ .size = 0 }  /* End of the table */
+};
+
+/*
+ * A80 has 40KiB SRAM A1 at 0x10000 where the SPL has to be loaded to. The
+ * secure SRAM B at 0x20000 is used as backup area for FEL stacks and data.
+ */
+sram_swap_buffers a80_sram_swap_buffers[] = {
+	{ .buf1 = 0x11800, .buf2 = 0x20000, .size = 0x800 },
+	{ .buf1 = 0x15400, .buf2 = 0x20800, .size = 0x18000 - 0x15400 },
+	{ .size = 0 }  /* End of the table */
+};
+
+soc_info_t soc_info_table[] = {
+	{
+		.soc_id       = 0x1623, /* Allwinner A10 */
+		.scratch_addr = 0x1000,
+		.thunk_addr   = 0xA200, .thunk_size = 0x200,
+		.swap_buffers = a10_a13_a20_sram_swap_buffers,
+		.needs_l2en   = true,
+		.sid_addr     = 0x01C23800,
+	},{
+		.soc_id       = 0x1625, /* Allwinner A13, R8 */
+		.scratch_addr = 0x1000,
+		.thunk_addr   = 0xA200, .thunk_size = 0x200,
+		.swap_buffers = a10_a13_a20_sram_swap_buffers,
+		.needs_l2en   = true,
+		.sid_addr     = 0x01C23800,
+	},{
+		.soc_id       = 0x1651, /* Allwinner A20 */
+		.scratch_addr = 0x1000,
+		.thunk_addr   = 0xA200, .thunk_size = 0x200,
+		.swap_buffers = a10_a13_a20_sram_swap_buffers,
+		.sid_addr     = 0x01C23800,
+	},{
+		.soc_id       = 0x1650, /* Allwinner A23 */
+		.scratch_addr = 0x1000,
+		.thunk_addr   = 0x46E00, .thunk_size = 0x200,
+		.swap_buffers = ar100_abusing_sram_swap_buffers,
+		.sid_addr     = 0x01C23800,
+	},{
+		.soc_id       = 0x1633, /* Allwinner A31 */
+		.scratch_addr = 0x1000,
+		.thunk_addr   = 0x22E00, .thunk_size = 0x200,
+		.swap_buffers = a31_sram_swap_buffers,
+	},{
+		.soc_id       = 0x1667, /* Allwinner A33, R16 */
+		.scratch_addr = 0x1000,
+		.thunk_addr   = 0x46E00, .thunk_size = 0x200,
+		.swap_buffers = ar100_abusing_sram_swap_buffers,
+		.sid_addr     = 0x01C23800,
+	},{
+		.soc_id       = 0x1689, /* Allwinner A64 */
+		.spl_addr     = 0x10000,
+		.scratch_addr = 0x11000,
+		.thunk_addr   = 0x1A200, .thunk_size = 0x200,
+		.swap_buffers = a64_sram_swap_buffers,
+		.sid_addr     = 0x01C14200,
+		.rvbar_reg    = 0x017000A0,
+	},{
+		.soc_id       = 0x1639, /* Allwinner A80 */
+		.spl_addr     = 0x10000,
+		.scratch_addr = 0x11000,
+		.thunk_addr   = 0x23400, .thunk_size = 0x200,
+		.swap_buffers = a80_sram_swap_buffers,
+	},{
+		.soc_id       = 0x1673, /* Allwinner A83T */
+		.scratch_addr = 0x1000,
+		.thunk_addr   = 0x46E00, .thunk_size = 0x200,
+		.swap_buffers = ar100_abusing_sram_swap_buffers,
+		.sid_addr     = 0x01C14200,
+	},{
+		.soc_id       = 0x1680, /* Allwinner H3, H2+ */
+		.scratch_addr = 0x1000,
+		.mmu_tt_addr  = 0x8000,
+		.thunk_addr   = 0xA200, .thunk_size = 0x200,
+		.swap_buffers = a10_a13_a20_sram_swap_buffers,
+		.sid_addr     = 0x01C14200,
+	},{
+		.soc_id       = 0x1718, /* Allwinner H5 */
+		.spl_addr     = 0x10000,
+		.scratch_addr = 0x11000,
+		.thunk_addr   = 0x1A200, .thunk_size = 0x200,
+		.swap_buffers = a64_sram_swap_buffers,
+		.sid_addr     = 0x01C14200,
+		.rvbar_reg    = 0x017000A0,
+	},{
+		.swap_buffers = NULL /* End of the table */
+	}
+};
+
+/*
+ * This generic record assumes BROM with similar properties to A10/A13/A20/A31,
+ * but no extra SRAM sections beyond 0x8000. It also assumes that the IRQ
+ * handler stack usage never exceeds 0x400 bytes.
+ *
+ * The users may or may not hope that the 0x7000-0x8000 area is also unused
+ * by the BROM and re-purpose it for the SPL stack.
+ *
+ * The size limit for the ".text + .data" sections is ~21 KiB.
+ */
+sram_swap_buffers generic_sram_swap_buffers[] = {
+	{ .buf1 = 0x1C00, .buf2 = 0x5800, .size = 0x400 },
+	{ .size = 0 }  /* End of the table */
+};
+
+soc_info_t generic_soc_info = {
+	.scratch_addr = 0x1000,
+	.thunk_addr   = 0x5680, .thunk_size = 0x180,
+	.swap_buffers = generic_sram_swap_buffers,
+};
+
+/* functions to retrieve SoC information */
+
+soc_info_t *get_soc_info_from_id(uint32_t soc_id)
+{
+	soc_info_t *result = NULL;
+	int i;
+
+	for (i = 0; soc_info_table[i].swap_buffers; i++)
+		if (soc_info_table[i].soc_id == soc_id) {
+			result = &soc_info_table[i];
+			break;
+		}
+
+	if (!result) {
+		printf("Warning: no 'soc_sram_info' data for your SoC (id=%04X)\n",
+		       soc_id);
+		result = &generic_soc_info;
+	}
+	return result;
+}
+
+soc_info_t *get_soc_info_from_version(struct aw_fel_version *buf)
+{
+	return get_soc_info_from_id(buf->soc_id);
+}

soc_info.h

+/*
+ * Copyright (C) 2015  Siarhei Siamashka <siarhei.siamashka@gmail.com>
+ * Copyright (C) 2016  Bernhard Nortmann <bernhard.nortmann@web.de>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef _SUNXI_TOOLS_SOC_INFO_H
+#define _SUNXI_TOOLS_SOC_INFO_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+/* SoC version information, as retrieved by the FEL protocol */
+struct aw_fel_version {
+	char signature[8];
+	uint32_t soc_id;	/* 0x00162300 */
+	uint32_t unknown_0a;	/* 1 */
+	uint16_t protocol;	/* 1 */
+	uint8_t  unknown_12;	/* 0x44 */
+	uint8_t  unknown_13;	/* 0x08 */
+	uint32_t scratchpad;	/* 0x7e00 */
+	uint32_t pad[2];	/* unused */
+} __attribute__((packed));
+
+/*
+ * The 'sram_swap_buffers' structure is used to describe information about
+ * pairwise memory regions in SRAM, the content of which needs to be exchanged
+ * before calling the U-Boot SPL code and then exchanged again before returning
+ * control back to the FEL code from the BROM.
+ */
+typedef struct {
+	uint32_t buf1; /* BROM buffer */
+	uint32_t buf2; /* backup storage location */
+	uint32_t size; /* buffer size */
+} sram_swap_buffers;
+
+/*
+ * Each SoC variant may have its own list of memory buffers to be exchanged
+ * and the information about the placement of the thunk code, which handles
+ * the transition of execution from the BROM FEL code to the U-Boot SPL and
+ * back.
+ *
+ * Note: the entries in the 'swap_buffers' tables need to be sorted by 'buf1'
+ * addresses. And the 'buf1' addresses are the BROM data buffers, while 'buf2'
+ * addresses are the intended backup locations.
+ *
+ * Also for performance reasons, we optionally want to have MMU enabled with
+ * optimal section attributes configured (the code from the BROM should use
+ * I-cache, writing data to the DRAM area should use write combining). The
+ * reason is that the BROM FEL protocol implementation moves data using the
+ * CPU somewhere on the performance critical path when transferring data over
+ * USB. The older SoC variants (A10/A13/A20/A31/A23) already have MMU enabled
+ * and we only need to adjust section attributes. The BROM in newer SoC variants
+ * (A33/A83T/H3) doesn't enable MMU any more, so we need to find some 16K of
+ * spare space in SRAM to place the translation table there and specify it as
+ * the 'mmu_tt_addr' field in the 'soc_sram_info' structure. The 'mmu_tt_addr'
+ * address must be 16K aligned.
+ */
+typedef struct {
+	uint32_t           soc_id;       /* ID of the SoC */
+	uint32_t           spl_addr;     /* SPL load address */
+	uint32_t           scratch_addr; /* A safe place to upload & run code */
+	uint32_t           thunk_addr;   /* Address of the thunk code */
+	uint32_t           thunk_size;   /* Maximal size of the thunk code */
+	bool               needs_l2en;   /* Set the L2EN bit */
+	uint32_t           mmu_tt_addr;  /* MMU translation table address */
+	uint32_t           sid_addr;     /* base address for SID_KEY[0-3] registers */
+	uint32_t           rvbar_reg;    /* MMIO address of RVBARADDR0_L register */
+	sram_swap_buffers *swap_buffers;
+} soc_info_t;
+
+
+soc_info_t *get_soc_info_from_id(uint32_t soc_id);
+soc_info_t *get_soc_info_from_version(struct aw_fel_version *buf);
+
+#endif /* _SUNXI_TOOLS_SOC_INFO_H */