1. 20 Apr, 2020 1 commit
  2. 28 Feb, 2017 1 commit
    • Andre Przywara's avatar
      fel: SMC workaround to enter "secure boot" FEL mode on some SoCs · 8c45b33e
      Andre Przywara authored
      
      
      If an SoC has the "secure boot" fuse burned, it will enter FEL mode in
      non-secure state, so with the SCR.NS bit set. Since in this mode the
      secure/non-secure state restrictions are actually observed, we suffer
      from several restrictions:
      - No access to the SID information (both via memory mapped and "register").
      - No access to secure SRAM (SRAM A2 on H3/A64/H5).
      - No access to the secure side of the GIC, so it can't be configured to
        be accessible from non-secure world.
      - No RMR trigger on ARMv8 cores to bring the core into AArch64.
      Those limitations make a board pretty useless for many applications.
      
      However it has been found out that a simple "smc" call will immediately
      return from monitor mode, but with the NS bit cleared, so access to all
      secure peripherals is suddenly possible.
      
      Add all the necessary support code for doing a runtime check and
      activating this workaround. Affected SoCs need to have the "smc"
      workaround enabled in their soc_info struct.
      Signed-off-by: default avatarAndre Przywara <osp@andrep.de>
      ["sunxi-fel smc" command changed to automatic detection by Siarhei]
      Signed-off-by: default avatarSiarhei Siamashka <siarhei.siamashka@gmail.com>
      8c45b33e
  3. 28 Dec, 2016 2 commits
  4. 29 Nov, 2016 1 commit
  5. 13 Nov, 2016 1 commit