Skip to content

GitLab

Switch branch/tag
  1. 21 Mar, 2016 2 commits
  3. 20 Mar, 2016 2 commits
  5. 17 Dec, 2015 3 commits
  7. 16 Dec, 2015 4 commits
  9. 07 Dec, 2015 4 commits
  11. 24 Nov, 2015 3 commits
  13. 19 Nov, 2015 2 commits
  15. 03 Oct, 2015 3 commits
  17. 13 Sep, 2015 2 commits
  19. 08 Sep, 2015 3 commits
  21. 29 Aug, 2015 2 commits
  23. 19 Aug, 2015 4 commits
  25. 01 Aug, 2015 1 commit
  27. 26 Feb, 2015 5 commits
    • Hans de Goede's avatar
      Add fel spl support for A23 · b80e7ce7
      Hans de Goede authored 
      
Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
Acked-by: default avatarSiarhei Siamashka <siarhei.siamashka@gmail.com>
      b80e7ce7
    • Siarhei Siamashka's avatar
      fel: Set the AUXCR L2EN bit for A10/A13 · f6a1382b
      Siarhei Siamashka authored 
      

This is needed to have feature parity with the normal boot mode,
where the L2EN bit in the CP15 Auxiliary Control Register is set
by the BROM code right from the start. And if L2EN is not set,
then the Linux system ends up booted with the L2 cache disabled.

According to the Cortex-A8 TRM, the L2 cache is only enabled when
both L2EN bit and the C bit from the CP15 Control Register c1 are
set. Because the BROM does not set the C bit, this change should
not affect the functionality of the FEL mode in any way.
Signed-off-by: default avatarSiarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: default avatarHans de Goede <hdegoede@redhat.com>
      f6a1382b
    • Siarhei Siamashka's avatar
      fel: Fix USB timeout on large transfers · eae30b2a
      Siarhei Siamashka authored 
      

Trying to use oversized initrd files (20 MB or more) can fail
with the "libusb usb_bulk_send error -1" error message.

To address this problem, we can split the transfer into smaller
chunks and the problem disappears. Effectively, this is a revert
of the older "fel: Increase timeout to 60 seconds instead of
splitting bulk transfers" commmit.
Signed-off-by: default avatarSiarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: default avatarHans de Goede <hdegoede@redhat.com>
      eae30b2a
    • Siarhei Siamashka's avatar
      fel: Faster USB transfers via 'fel write' to DRAM · e4b3da2b
      Siarhei Siamashka authored 
      

By adjusting the MMU translation table before restoring it
and by enabling the I-cache with branch prediction, we can
improve performance. The DRAM area (0x40000000-0xC0000000)
becomes write-combine mapped and the BROM code becomes mapped
as cacheable memory. This is expected to be safe and should
not cause any coherency problems.

Transfer speed improvements:

A10  : ~330 KB/s -> ~600 KB/s
A13  : ~330 KB/s -> ~600 KB/s
A20  : ~320 KB/s -> ~960 KB/s
A31s : ~250 KB/s -> ~510 KB/s
Signed-off-by: default avatarSiarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: default avatarHans de Goede <hdegoede@redhat.com>
      e4b3da2b
    • Siarhei Siamashka's avatar
      fel: Disable MMU to get more SRAM space and fix A13 problems · dc6c801c
      Siarhei Siamashka authored 
      

The FEL BROM code has the MMU enabled for some reason (while
I-cache and D-cache are disabled). Most likely the intention was
to get a somewhat better performance. Everything is mapped as
TEXCB=00000 (strongly ordered), except for the 0x00000000 (SRAM)
and 0xFFF00000 (BROM) sections, which are mapped as TEXCB=00100
(normal uncached memory).

This becomes a problem for the A13 SoC, because it has less SRAM
than the other chips. A13 stores the MMU addresses translation
table at 0x8000 and uses up 16 KiB of the SRAM space there (while
the A10, A20 and A31s keep the MMU table in the secure SRAM at
0x20000). And because the 'spl' command needs space for backing
up the FEL stacks, it was clashing with the MMU table.

The solution is simple. We just backup the addresses translation
table and disable the MMU before running the SPL. And then restore
it back to the original state. This fixes problems on A13.

Re-enabling the MMU in the end is only necessary to avoid performance
losses. For example, the transfer speed of the 'fel write' command
on A20 would drop from ~320 KB/s to ~260 KB/s without MMU.
Signed-off-by: default avatarSiarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: default avatarHans de Goede <hdegoede@redhat.com>
      dc6c801c