plat.ld.S 2.1 KB
Newer Older
1
2
3
/*
 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
 *
dp-arm's avatar
dp-arm committed
4
 * SPDX-License-Identifier: BSD-3-Clause
5
6
7
8
 */
#ifndef __ROCKCHIP_PLAT_LD_S__
#define __ROCKCHIP_PLAT_LD_S__

9
10
#include <xlat_tables_defs.h>

11
12
MEMORY {
    SRAM (rwx): ORIGIN = SRAM_BASE, LENGTH = SRAM_SIZE
Lin Huang's avatar
Lin Huang committed
13
    PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE
14
15
16
17
18
}

SECTIONS
{
	. = SRAM_BASE;
19
	ASSERT(. == ALIGN(PAGE_SIZE),
20
21
22
23
24
		"SRAM_BASE address is not aligned on a page boundary.")

	/*
	 * The SRAM space allocation for RK3399
	 * ----------------
25
26
	 * | m0 code bin
	 * ----------------
27
28
29
30
31
	 * | sram text
	 * ----------------
	 * | sram data
	 * ----------------
	 */
32
	.incbin_sram : ALIGN(PAGE_SIZE) {
33
34
		__sram_incbin_start = .;
		*(.sram.incbin)
35
		 __sram_incbin_real_end = .;
36
		. = ALIGN(PAGE_SIZE);
37
38
		__sram_incbin_end = .;
	} >SRAM
39
40
	ASSERT((__sram_incbin_real_end - __sram_incbin_start) <=
		SRAM_BIN_LIMIT, ".incbin_sram has exceeded its limit")
41

42
	.text_sram : ALIGN(PAGE_SIZE) {
43
44
45
		__bl31_sram_text_start = .;
		*(.sram.text)
		*(.sram.rodata)
46
		__bl31_sram_text_real_end = .;
47
		. = ALIGN(PAGE_SIZE);
48
49
		__bl31_sram_text_end = .;
	} >SRAM
50
51
	ASSERT((__bl31_sram_text_real_end - __bl31_sram_text_start) <=
		SRAM_TEXT_LIMIT, ".text_sram has exceeded its limit")
52

53
	.data_sram : ALIGN(PAGE_SIZE) {
54
55
		__bl31_sram_data_start = .;
		*(.sram.data)
56
		__bl31_sram_data_real_end = .;
57
		. = ALIGN(PAGE_SIZE);
58
59
		__bl31_sram_data_end = .;
	} >SRAM
60
61
	ASSERT((__bl31_sram_data_real_end - __bl31_sram_data_start) <=
		SRAM_DATA_LIMIT, ".data_sram has exceeded its limit")
Lin Huang's avatar
Lin Huang committed
62

63
	.stack_sram : ALIGN(PAGE_SIZE) {
Lin Huang's avatar
Lin Huang committed
64
		__bl31_sram_stack_start = .;
65
		. += PAGE_SIZE;
Lin Huang's avatar
Lin Huang committed
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
		__bl31_sram_stack_end = .;
	} >SRAM

	. = PMUSRAM_BASE;

	/*
	 * pmu_cpuson_entrypoint request address
	 * align 64K when resume, so put it in the
	 * start of pmusram
	 */
	.pmusram : {
		ASSERT(. == ALIGN(64 * 1024),
			".pmusram.entry request 64K aligned.");
		*(.pmusram.entry)
		__bl31_pmusram_text_start = .;
		*(.pmusram.text)
		*(.pmusram.rodata)
		__bl31_pmusram_text_end = .;
		__bl31_pmusram_data_start = .;
		*(.pmusram.data)
		__bl31_pmusram_data_end = .;

	} >PMUSRAM
89
90
91
}

#endif /* __ROCKCHIP_PLAT_LD_S__ */