• Achin Gupta's avatar
    Factor out translation table setup in ARM FVP port · a0cd989d
    Achin Gupta authored
    This patch factors out the ARM FVP specific code to create MMU
    translation tables so that it is possible for a boot loader stage to
    create a different set of tables instead of using the default ones.
    The default translation tables are created with the assumption that
    the calling boot loader stage executes out of secure SRAM. This might
    not be true for the BL3_2 stage in the future.
    
    A boot loader stage can define the `fill_xlation_tables()` function as
    per its requirements. It returns a reference to the level 1
    translation table which is used by the common platform code to setup
    the TTBR_EL3.
    
    This patch is a temporary solution before a larger rework of
    translation table creation logic is introduced.
    
    Change-Id: I09a075d5da16822ee32a411a9dbe284718fb4ff6
    a0cd989d
bl1.mk 1.98 KB
#
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vpath			%.c	plat/${PLAT}		\
				plat/${PLAT}/${ARCH}	\
				common			\
				lib			\
				arch/${ARCH}		\
				lib/arch/${ARCH}	\
				${PLAT_BL1_C_VPATH}

vpath			%.S	arch/${ARCH}/cpu	\
				plat/common/${ARCH}	\
				plat/${PLAT}/${ARCH}	\
				include			\
				lib/arch/${ARCH}	\
				${PLAT_BL1_S_VPATH}

BL1_OBJS		+=	bl1_arch_setup.o	\
				bl1_entrypoint.o	\
				early_exceptions.o	\
				bl1_main.o		\
				cpu_helpers.o

BL1_ENTRY_POINT		:=	reset_handler
BL1_MAPFILE		:=	bl1.map
BL1_LINKERFILE		:=	bl1.ld