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  • Oliver Swede's avatar
    plat/arm/board/arm_fpga: Initialize the System Counter · 2d696d18
    Oliver Swede authored 
    

This sets the frequency of the system counter so that the Delay Timer
driver programs the correct value to CNTCRL. This value depends on
the FPGA image being used, and is 10MHz for the initial test image.
Once configured, the BL31 platform setup sequence then enables the
system counter.
Signed-off-by: default avatarOliver Swede <oli.swede@arm.com>
Change-Id: Ieb036a36fd990f350b5953357424a255b8ac5d5a
    2d696d18
fpga_bl31_setup.c 1.93 KB