• Lin Huang's avatar
    rockchip/rk3399: fix DRAM gate training issue · a9059b96
    Lin Huang authored
    
    
    The differential signal of DQS need keep low level
    before gate training. It need enable RPULL and disable
    PHY side ODT to ensure it when do gate training.
    But it can not access the PHY registers to do it when
    perform DFS.So the workaroud as below: It is ensure that
    the PHY's read gate is landing somewhere in the incoming
    DQS's pulses before it starts searching for pre-amble window.
    It need get the rddqs_delay_ps to calculate the start point
    of gate training for DFS.
    
    Change-Id: I79eabcf4ec9a9c8f4539f68a51f22afba49c72fe
    Signed-off-by: default avatarLin Huang <hl@rock-chips.com>
    a9059b96
dfs.c 67.1 KB