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Pali Rohár authored
The delay loop executes 3 instructions. These 3 instructions are executed in 2 processor ticks and 30000 iterations on a 600 MHz CPU should yield approximately 100 us. This means we are waiting 2 ms, not 20 ms, for TX FIFO to be empty. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I2cccad405bcc73cd6d1062adc0205c405c16c15f
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