• Vikram Kanigiri's avatar
    Tegra: Perform cache maintenance on video carveout memory · e3616819
    Vikram Kanigiri authored
    Currently, the non-overlapping video memory carveout region is cleared after
    disabling the MMU at EL3. If at any exception level the carveout region is being
    marked as cacheable, this zeroing of memory will not have an affect on the
    cached lines. Hence, we first invalidate the dirty lines and update the memory
    and invalidate again so that both caches and memory is zeroed out.
    
    Change-Id: If3b2d139ab7227f6799c0911d59e079849dc86aa
    e3616819
memctrl.c 6.62 KB