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  • Joel Hutton's avatar
    Add note about erratum 814220 for A7 · f999faca
    Joel Hutton authored 
    

On Cortex-A7 an L2 set/way cache maintenance operation can overtake
an L1 set/way cache maintenance operation. The mitigation for this is
to use a `DSB` instruction before changing cache. The cache cleaning
code happens to already be doing this, so only a comment was added.

Change-Id: Ia1ffb8ca8b6bbbba422ed6f6818671ef9fe02d90
Signed-off-by: default avatarJoel Hutton <Joel.Hutton@Arm.com>
    f999faca
cache_helpers.S 6.36 KB